forked from suyu/suyu
armdefs: Move some defines over to enums
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Lioncash
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28702cbfeb
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3dfef1701c
1 changed files with 106 additions and 125 deletions
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@ -395,53 +395,41 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
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#define DIFF_WRITE 0
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typedef ARMul_State arm_core_t;
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#define ResetPin NresetSig
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#define FIQPin NfiqSig
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#define IRQPin NirqSig
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#define AbortPin abortSig
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#define TransPin NtransSig
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#define BigEndPin bigendSig
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#define Prog32Pin prog32Sig
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#define Data32Pin data32Sig
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#define LateAbortPin lateabtSig
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/***************************************************************************\
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* Types of ARM we know about *
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\***************************************************************************/
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/* The bitflags */
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#define ARM_Fix26_Prop 0x01
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#define ARM_Nexec_Prop 0x02
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#define ARM_Debug_Prop 0x10
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#define ARM_Isync_Prop ARM_Debug_Prop
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#define ARM_Lock_Prop 0x20
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#define ARM_v4_Prop 0x40
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#define ARM_v5_Prop 0x80
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#define ARM_v6_Prop 0xc0
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enum {
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ARM_Fix26_Prop = 0x01,
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ARM_Nexec_Prop = 0x02,
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ARM_Debug_Prop = 0x10,
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ARM_Isync_Prop = ARM_Debug_Prop,
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ARM_Lock_Prop = 0x20,
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ARM_v4_Prop = 0x40,
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ARM_v5_Prop = 0x80,
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ARM_v6_Prop = 0xc0,
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#define ARM_v5e_Prop 0x100
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#define ARM_XScale_Prop 0x200
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#define ARM_ep9312_Prop 0x400
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#define ARM_iWMMXt_Prop 0x800
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#define ARM_PXA27X_Prop 0x1000
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#define ARM_v7_Prop 0x2000
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ARM_v5e_Prop = 0x100,
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ARM_XScale_Prop = 0x200,
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ARM_ep9312_Prop = 0x400,
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ARM_iWMMXt_Prop = 0x800,
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ARM_PXA27X_Prop = 0x1000,
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ARM_v7_Prop = 0x2000,
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/* ARM2 family */
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#define ARM2 (ARM_Fix26_Prop)
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#define ARM2as ARM2
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#define ARM61 ARM2
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#define ARM3 ARM2
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// ARM2 family
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ARM2 = ARM_Fix26_Prop,
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ARM2as = ARM2,
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ARM61 = ARM2,
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ARM3 = ARM2,
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#ifdef ARM60 /* previous definition in armopts.h */
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#undef ARM60
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#endif
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/* ARM6 family */
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#define ARM6 (ARM_Lock_Prop)
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#define ARM60 ARM6
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#define ARM600 ARM6
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#define ARM610 ARM6
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#define ARM620 ARM6
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// ARM6 family
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ARM6 = ARM_Lock_Prop,
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ARM60 = ARM6,
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ARM600 = ARM6,
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ARM610 = ARM6,
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ARM620 = ARM6
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};
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/***************************************************************************\
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@ -456,41 +444,44 @@ typedef ARMul_State arm_core_t;
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* The hardware vector addresses *
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\***************************************************************************/
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#define ARMResetV 0L
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#define ARMUndefinedInstrV 4L
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#define ARMSWIV 8L
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#define ARMPrefetchAbortV 12L
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#define ARMDataAbortV 16L
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#define ARMAddrExceptnV 20L
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#define ARMIRQV 24L
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#define ARMFIQV 28L
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#define ARMErrorV 32L /* This is an offset, not an address ! */
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enum {
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ARMResetV = 0,
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ARMUndefinedInstrV = 4,
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ARMSWIV = 8,
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ARMPrefetchAbortV = 12,
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ARMDataAbortV = 16,
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ARMAddrExceptnV = 20,
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ARMIRQV = 24,
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ARMFIQV = 28,
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ARMErrorV = 32, // This is an offset, not an address!
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#define ARMul_ResetV ARMResetV
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#define ARMul_UndefinedInstrV ARMUndefinedInstrV
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#define ARMul_SWIV ARMSWIV
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#define ARMul_PrefetchAbortV ARMPrefetchAbortV
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#define ARMul_DataAbortV ARMDataAbortV
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#define ARMul_AddrExceptnV ARMAddrExceptnV
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#define ARMul_IRQV ARMIRQV
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#define ARMul_FIQV ARMFIQV
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ARMul_ResetV = ARMResetV,
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ARMul_UndefinedInstrV = ARMUndefinedInstrV,
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ARMul_SWIV = ARMSWIV,
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ARMul_PrefetchAbortV = ARMPrefetchAbortV,
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ARMul_DataAbortV = ARMDataAbortV,
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ARMul_AddrExceptnV = ARMAddrExceptnV,
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ARMul_IRQV = ARMIRQV,
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ARMul_FIQV = ARMFIQV
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};
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/***************************************************************************\
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* Mode and Bank Constants *
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\***************************************************************************/
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#define USER26MODE 0L
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#define FIQ26MODE 1L
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#define IRQ26MODE 2L
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#define SVC26MODE 3L
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#define USER32MODE 16L
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#define FIQ32MODE 17L
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#define IRQ32MODE 18L
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#define SVC32MODE 19L
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#define ABORT32MODE 23L
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#define UNDEF32MODE 27L
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//chy 2006-02-15 add system32 mode
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#define SYSTEM32MODE 31L
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enum {
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USER26MODE = 0,
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FIQ26MODE = 1,
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IRQ26MODE = 2,
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SVC26MODE = 3,
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USER32MODE = 16,
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FIQ32MODE = 17,
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IRQ32MODE = 18,
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SVC32MODE = 19,
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ABORT32MODE = 23,
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UNDEF32MODE = 27,
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SYSTEM32MODE = 31
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};
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#define ARM32BITMODE (state->Mode > 3)
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#define ARM26BITMODE (state->Mode <= 3)
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@ -499,14 +490,17 @@ typedef ARMul_State arm_core_t;
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#define ARMul_MODE32BIT ARM32BITMODE
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#define ARMul_MODE26BIT ARM26BITMODE
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#define USERBANK 0
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#define FIQBANK 1
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#define IRQBANK 2
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#define SVCBANK 3
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#define ABORTBANK 4
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#define UNDEFBANK 5
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#define DUMMYBANK 6
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#define SYSTEMBANK USERBANK
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enum {
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USERBANK = 0,
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FIQBANK = 1,
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IRQBANK = 2,
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SVCBANK = 3,
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ABORTBANK = 4,
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UNDEFBANK = 5,
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DUMMYBANK = 6,
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SYSTEMBANK = USERBANK
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};
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#define BANK_CAN_ACCESS_SPSR(bank) \
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((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
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@ -613,40 +607,44 @@ extern ARMword ARMul_MemAccess(ARMul_State* state, ARMword, ARMword,
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* Definitons of things in the co-processor interface *
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\***************************************************************************/
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#define ARMul_FIRST 0
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#define ARMul_TRANSFER 1
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#define ARMul_BUSY 2
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#define ARMul_DATA 3
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#define ARMul_INTERRUPT 4
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#define ARMul_DONE 0
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#define ARMul_CANT 1
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#define ARMul_INC 3
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enum {
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ARMul_FIRST = 0,
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ARMul_TRANSFER = 1,
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ARMul_BUSY = 2,
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ARMul_DATA = 3,
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ARMul_INTERRUPT = 4,
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ARMul_DONE = 0,
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ARMul_CANT = 1,
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ARMul_INC = 3
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};
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#define ARMul_CP13_R0_FIQ 0x1
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#define ARMul_CP13_R0_IRQ 0x2
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#define ARMul_CP13_R8_PMUS 0x1
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enum {
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ARMul_CP13_R0_FIQ = 0x1,
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ARMul_CP13_R0_IRQ = 0x2,
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ARMul_CP13_R8_PMUS = 0x1,
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#define ARMul_CP14_R0_ENABLE 0x0001
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#define ARMul_CP14_R0_CLKRST 0x0004
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#define ARMul_CP14_R0_CCD 0x0008
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#define ARMul_CP14_R0_INTEN0 0x0010
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#define ARMul_CP14_R0_INTEN1 0x0020
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#define ARMul_CP14_R0_INTEN2 0x0040
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#define ARMul_CP14_R0_FLAG0 0x0100
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#define ARMul_CP14_R0_FLAG1 0x0200
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#define ARMul_CP14_R0_FLAG2 0x0400
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#define ARMul_CP14_R10_MOE_IB 0x0004
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#define ARMul_CP14_R10_MOE_DB 0x0008
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#define ARMul_CP14_R10_MOE_BT 0x000c
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#define ARMul_CP15_R1_ENDIAN 0x0080
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#define ARMul_CP15_R1_ALIGN 0x0002
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#define ARMul_CP15_R5_X 0x0400
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#define ARMul_CP15_R5_ST_ALIGN 0x0001
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#define ARMul_CP15_R5_IMPRE 0x0406
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#define ARMul_CP15_R5_MMU_EXCPT 0x0400
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#define ARMul_CP15_DBCON_M 0x0100
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#define ARMul_CP15_DBCON_E1 0x000c
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#define ARMul_CP15_DBCON_E0 0x0003
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ARMul_CP14_R0_ENABLE = 0x0001,
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ARMul_CP14_R0_CLKRST = 0x0004,
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ARMul_CP14_R0_CCD = 0x0008,
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ARMul_CP14_R0_INTEN0 = 0x0010,
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ARMul_CP14_R0_INTEN1 = 0x0020,
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ARMul_CP14_R0_INTEN2 = 0x0040,
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ARMul_CP14_R0_FLAG0 = 0x0100,
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ARMul_CP14_R0_FLAG1 = 0x0200,
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ARMul_CP14_R0_FLAG2 = 0x0400,
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ARMul_CP14_R10_MOE_IB = 0x0004,
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ARMul_CP14_R10_MOE_DB = 0x0008,
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ARMul_CP14_R10_MOE_BT = 0x000c,
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ARMul_CP15_R1_ENDIAN = 0x0080,
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ARMul_CP15_R1_ALIGN = 0x0002,
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ARMul_CP15_R5_X = 0x0400,
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ARMul_CP15_R5_ST_ALIGN = 0x0001,
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ARMul_CP15_R5_IMPRE = 0x0406,
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ARMul_CP15_R5_MMU_EXCPT = 0x0400,
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ARMul_CP15_DBCON_M = 0x0100,
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ARMul_CP15_DBCON_E1 = 0x000c,
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ARMul_CP15_DBCON_E0 = 0x0003
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};
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extern unsigned ARMul_CoProInit(ARMul_State* state);
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extern void ARMul_CoProExit(ARMul_State* state);
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@ -675,12 +673,9 @@ extern unsigned ARMul_OSHandleSWI(ARMul_State* state, ARMword number);
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}
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#endif
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extern ARMword ARMul_OSLastErrorP(ARMul_State* state);
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extern ARMword ARMul_Debug(ARMul_State* state, ARMword pc, ARMword instr);
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extern unsigned ARMul_OSException(ARMul_State* state, ARMword vector, ARMword pc);
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extern int rdi_log;
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enum ConditionCode {
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EQ = 0,
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@ -729,12 +724,6 @@ enum ConditionCode {
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#define IFFLAGS state->IFFlags
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#endif //VFLAG
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#define FLAG_MASK 0xf0000000
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#define NBIT_SHIFT 31
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#define ZBIT_SHIFT 30
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#define CBIT_SHIFT 29
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#define VBIT_SHIFT 28
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#define SKYEYE_OUTREGS(fd) { fprintf ((fd), "R %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,C %x,S %x,%x,%x,%x,%x,%x,%x,M %x,B %x,E %x,I %x,P %x,T %x,L %x,D %x,",\
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state->Reg[0],state->Reg[1],state->Reg[2],state->Reg[3], \
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state->Reg[4],state->Reg[5],state->Reg[6],state->Reg[7], \
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@ -778,14 +767,6 @@ RUn %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",\
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state->RegBank[5][12],state->RegBank[5][13],state->RegBank[5][14],state->RegBank[5][15] \
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);}
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#define SA1110 0x6901b110
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#define SA1100 0x4401a100
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#define PXA250 0x69052100
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#define PXA270 0x69054110
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//#define PXA250 0x69052903
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// 0x69052903; //PXA250 B1 from intel 278522-001.pdf
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extern bool AddOverflow(ARMword, ARMword, ARMword);
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extern bool SubOverflow(ARMword, ARMword, ARMword);
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