1
0
Fork 0
forked from suyu/suyu
suyu/src/core/arm/dynarmic
ReinUsesLisp b3587102d1 core/memory: Read and write page table atomically
Squash attributes into the pointer's integer, making them an uintptr_t
pair containing 2 bits at the bottom and then the pointer. These bits
are currently unused thanks to alignment requirements.

Configure Dynarmic to mask out these bits on pointer reads.

While we are at it, remove some unused attributes carried over from
Citra.

Read/Write and other hot functions use a two step unpacking process that
is less readable to stop MSVC from emitting an extra AND instruction in
the hot path:

 mov         rdi,rcx
 shr         rdx,0Ch
 mov         r8,qword ptr [rax+8]
 mov         rax,qword ptr [r8+rdx*8]
 mov         rdx,rax
-and         al,3
 and         rdx,0FFFFFFFFFFFFFFFCh
 je          Core::Memory::Memory::Impl::Read<unsigned char>
 mov         rax,qword ptr [vaddr]
 movzx       eax,byte ptr [rdx+rax]
2020-12-29 21:54:49 -03:00
..
arm_dynarmic_32.cpp core/memory: Read and write page table atomically 2020-12-29 21:54:49 -03:00
arm_dynarmic_32.h core: arm: Implement InvalidateCacheRange for CPU cache invalidation. 2020-11-29 01:31:52 -08:00
arm_dynarmic_64.cpp core/memory: Read and write page table atomically 2020-12-29 21:54:49 -03:00
arm_dynarmic_64.h core: arm: Implement InvalidateCacheRange for CPU cache invalidation. 2020-11-29 01:31:52 -08:00
arm_dynarmic_cp15.cpp General: Make use of std::nullopt where applicable 2020-09-22 17:32:33 -04:00
arm_dynarmic_cp15.h arm_dynarmic_cp15: Initialize member variables 2020-09-17 13:03:49 -04:00
arm_exclusive_monitor.cpp ARM: Update Dynarmic and Setup A32 according to latest interface. 2020-06-27 11:36:26 -04:00
arm_exclusive_monitor.h ARM: Update Dynarmic and Setup A32 according to latest interface. 2020-06-27 11:36:26 -04:00