217 lines
6.4 KiB
C++
217 lines
6.4 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include "common/common_types.h"
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#include "common/bit_field.h"
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namespace GPU {
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static const u32 kFrameCycles = 268123480 / 60; ///< 268MHz / 60 frames per second
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static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of instructions/frame
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struct Registers {
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enum Id : u32 {
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FramebufferTopSize = 0x1EF0045C,
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FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left
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FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left
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FramebufferTopFormat = 0x1EF00470,
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FramebufferTopSwapBuffers = 0x1EF00478,
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FramebufferTopStride = 0x1EF00490, // framebuffer row stride?
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FramebufferTopRight1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right
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FramebufferTopRight2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right
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FramebufferSubSize = 0x1EF0055C,
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FramebufferSubLeft1 = 0x1EF00568, // Sub LCD, first framebuffer
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FramebufferSubLeft2 = 0x1EF0056C, // Sub LCD, second framebuffer
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FramebufferSubFormat = 0x1EF00570,
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FramebufferSubSwapBuffers = 0x1EF00578,
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FramebufferSubStride = 0x1EF00590, // framebuffer row stride?
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FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer
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FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer
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DisplayInputBufferAddr = 0x1EF00C00,
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DisplayOutputBufferAddr = 0x1EF00C04,
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DisplayOutputBufferSize = 0x1EF00C08,
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DisplayInputBufferSize = 0x1EF00C0C,
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DisplayTransferFlags = 0x1EF00C10,
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// Unknown??
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DisplayTriggerTransfer = 0x1EF00C18,
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CommandListSize = 0x1EF018E0,
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CommandListAddress = 0x1EF018E8,
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ProcessCommandList = 0x1EF018F0,
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};
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enum class FramebufferFormat : u32 {
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RGBA8 = 0,
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RGB8 = 1,
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RGB565 = 2,
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RGB5A1 = 3,
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RGBA4 = 4,
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};
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// TODO: Move these into the framebuffer struct
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u32 framebuffer_top_left_1;
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u32 framebuffer_top_left_2;
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u32 framebuffer_top_right_1;
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u32 framebuffer_top_right_2;
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u32 framebuffer_sub_left_1;
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u32 framebuffer_sub_left_2;
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u32 framebuffer_sub_right_1;
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u32 framebuffer_sub_right_2;
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struct FrameBufferConfig {
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union {
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u32 size;
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BitField< 0, 16, u32> width;
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BitField<16, 16, u32> height;
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};
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union {
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u32 format;
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BitField< 0, 3, FramebufferFormat> color_format;
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};
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union {
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u32 active_fb;
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BitField<0, 1, u32> second_fb_active;
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};
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u32 stride;
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};
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FrameBufferConfig top_framebuffer;
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FrameBufferConfig sub_framebuffer;
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struct {
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u32 input_address;
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u32 output_address;
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inline u32 GetPhysicalInputAddress() const {
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return input_address * 8;
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}
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inline u32 GetPhysicalOutputAddress() const {
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return output_address * 8;
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}
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union {
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u32 output_size;
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BitField< 0, 16, u32> output_width;
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BitField<16, 16, u32> output_height;
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};
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union {
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u32 input_size;
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BitField< 0, 16, u32> input_width;
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BitField<16, 16, u32> input_height;
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};
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union {
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u32 flags;
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BitField< 0, 1, u32> flip_data;
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BitField< 8, 3, FramebufferFormat> input_format;
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BitField<12, 3, FramebufferFormat> output_format;
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BitField<16, 1, u32> output_tiled;
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};
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u32 unknown;
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u32 trigger;
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} display_transfer;
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u32 command_list_size;
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u32 command_list_address;
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u32 command_processing_enabled;
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};
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extern Registers g_regs;
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enum {
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TOP_ASPECT_X = 0x5,
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TOP_ASPECT_Y = 0x3,
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TOP_HEIGHT = 240,
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TOP_WIDTH = 400,
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BOTTOM_WIDTH = 320,
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// Physical addresses in FCRAM (chosen arbitrarily)
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PADDR_TOP_LEFT_FRAME1 = 0x201D4C00,
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PADDR_TOP_LEFT_FRAME2 = 0x202D4C00,
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PADDR_TOP_RIGHT_FRAME1 = 0x203D4C00,
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PADDR_TOP_RIGHT_FRAME2 = 0x204D4C00,
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PADDR_SUB_FRAME1 = 0x205D4C00,
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PADDR_SUB_FRAME2 = 0x206D4C00,
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// Physical addresses in FCRAM used by ARM9 applications
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/* PADDR_TOP_LEFT_FRAME1 = 0x20184E60,
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PADDR_TOP_LEFT_FRAME2 = 0x201CB370,
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PADDR_TOP_RIGHT_FRAME1 = 0x20282160,
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PADDR_TOP_RIGHT_FRAME2 = 0x202C8670,
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PADDR_SUB_FRAME1 = 0x202118E0,
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PADDR_SUB_FRAME2 = 0x20249CF0,*/
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// Physical addresses in VRAM
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// TODO: These should just be deduced from the ones above
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PADDR_VRAM_TOP_LEFT_FRAME1 = 0x181D4C00,
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PADDR_VRAM_TOP_LEFT_FRAME2 = 0x182D4C00,
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PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x183D4C00,
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PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x184D4C00,
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PADDR_VRAM_SUB_FRAME1 = 0x185D4C00,
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PADDR_VRAM_SUB_FRAME2 = 0x186D4C00,
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// Physical addresses in VRAM used by ARM9 applications
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/* PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370,
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PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x18282160,
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PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x182C8670,
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PADDR_VRAM_SUB_FRAME1 = 0x182118E0,
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PADDR_VRAM_SUB_FRAME2 = 0x18249CF0,*/
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};
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/// Framebuffer location
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enum FramebufferLocation {
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FRAMEBUFFER_LOCATION_UNKNOWN, ///< Framebuffer location is unknown
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FRAMEBUFFER_LOCATION_FCRAM, ///< Framebuffer is in the GSP heap
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FRAMEBUFFER_LOCATION_VRAM, ///< Framebuffer is in VRAM
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};
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/**
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* Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM
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* @param
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*/
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void SetFramebufferLocation(const FramebufferLocation mode);
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/**
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* Gets a read-only pointer to a framebuffer in memory
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* @param address Physical address of framebuffer
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* @return Returns const pointer to raw framebuffer
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*/
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const u8* GetFramebufferPointer(const u32 address);
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/**
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* Gets the location of the framebuffers
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*/
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const FramebufferLocation GetFramebufferLocation();
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template <typename T>
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inline void Read(T &var, const u32 addr);
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template <typename T>
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inline void Write(u32 addr, const T data);
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/// Update hardware
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void Update();
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/// Initialize hardware
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void Init();
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/// Shutdown hardware
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void Shutdown();
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} // namespace
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