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Author SHA1 Message Date
Fernando Sahmkow
555866f8dc Core Timing: Rework Core Timing to run all cores evenly. 2019-10-09 12:30:31 -04:00
bunnei
dc29919bbe
Revert "arm_dynarmic: Check if jit is nullptr when preparing reschedule" 2019-09-29 21:54:19 -04:00
bunnei
28538bba9c
Merge pull request #2574 from DarkLordZach/dynarmic-jit-nullptr
arm_dynarmic: Check if jit is nullptr when preparing reschedule
2019-09-29 21:44:10 -04:00
Lioncash
093e5440e2 core: Remove CurrentArmInterface() global accessor
Replaces the final usage of the global accessor function and removes it.
Removes one more enabler of global state.
2019-07-12 21:48:49 -04:00
Lioncash
70624e1c1d core/arm: Remove obsolete Unicorn memory mapping
This was initially necessary when AArch64 JIT emulation was in its
infancy and all memory-related instructions weren't implemented.

Given the JIT now has all of these facilities implemented, we can remove
these functions from the CPU interface.
2019-07-11 05:35:46 -04:00
Zach Hilman
425cdf946c arm_dynarmic: Check if jit is nullptr when preparing reschedule
Prevents crash with multiprocess loading.
2019-06-10 00:14:25 -04:00
Zach Hilman
b77fde7c5c loader: Move NSO module tracking to AppLoader
Also cleanup of general stuff
2019-05-26 11:40:46 -04:00
Zach Hilman
5574be21cc arm_interface: Expand backtrace generation
Returns results as a vector of entries for further processing. Logs addresses, offsets, and mangled name.
2019-05-25 16:06:53 -04:00
Lioncash
f2331a804a core/cpu_core_manager: Create threads separately from initialization.
Our initialization process is a little wonky than one would expect when
it comes to code flow. We initialize the CPU last, as opposed to
hardware, where the CPU obviously needs to be first, otherwise nothing
else would work, and we have code that adds checks to get around this.

For example, in the page table setting code, we check to see if the
system is turned on before we even notify the CPU instances of a page
table switch. This results in dead code (at the moment), because the
only time a page table switch will occur is when the system is *not*
running, preventing the emulated CPU instances from being notified of a
page table switch in a convenient manner (technically the code path
could be taken, but we don't emulate the process creation svc handlers
yet).

This moves the threads creation into its own member function of the core
manager and restores a little order (and predictability) to our
initialization process.

Previously, in the multi-threaded cases, we'd kick off several threads
before even the main kernel process was created and ready to execute (gross!).
Now the initialization process is like so:

Initialization:
  1. Timers

  2. CPU

  3. Kernel

  4. Filesystem stuff (kind of gross, but can be amended trivially)

  5. Applet stuff (ditto in terms of being kind of gross)

  6. Main process (will be moved into the loading step in a following
                   change)

  7. Telemetry (this should be initialized last in the future).

  8. Services (4 and 5 should ideally be alongside this).

  9. GDB (gross. Uses namespace scope state. Needs to be refactored into a
          class or booted altogether).

  10. Renderer

  11. GPU (will also have its threads created in a separate step in a
           following change).

Which... isn't *ideal* per-se, however getting rid of the wonky
intertwining of CPU state initialization out of this mix gets rid of
most of the footguns when it comes to our initialization process.
2019-04-11 22:11:40 -04:00
Lioncash
b117ca5fce kernel/svc: Deglobalize the supervisor call handlers
Adjusts the interface of the wrappers to take a system reference, which
allows accessing a system instance without using the global accessors.

This also allows getting rid of all global accessors within the
supervisor call handling code. While this does make the wrappers
themselves slightly more noisy, this will be further cleaned up in a
follow-up. This eliminates the global system accessors in the current
code while preserving the existing interface.
2019-04-07 20:30:05 -04:00
Lioncash
a6a82bb004 arm/arm_dynarmic: Remove unnecessary current_page_table member
Given the page table will always be guaranteed to be that of whatever
the current process is, we no longer need to keep this around.
2019-04-07 02:43:51 -04:00
bunnei
54c7e8e40e
Merge pull request #2240 from FearlessTobi/port-4651
Port citra-emu/citra#4651: "gdbstub: Fix some bugs in IsMemoryBreak() and ServeBreak. Add workaround to let watchpoints break into GDB."
2019-04-05 23:46:37 -04:00
Lioncash
5b0a9f8ba8 core: Add missing override specifiers where applicable
Applies the override specifier where applicable. In the case of
destructors that are  defaulted in their definition, they can
simply be removed.

This also removes the unnecessary inclusions being done in audin_u and
audrec_u, given their close proximity.
2019-04-04 12:19:44 -04:00
bunnei
93da8e0abf core: Move PageTable struct into Common. 2019-03-16 22:05:40 -04:00
Dimitri A
0e7ad1c367 gdbstub: Fix some bugs in IsMemoryBreak() and ServeBreak. Add workaround to let watchpoints break into GDB. (#4651)
* gdbstub: fix IsMemoryBreak() returning false while connected to client

As a result, the only existing codepath for a memory watchpoint hit to break into GDB (InterpeterMainLoop, GDB_BP_CHECK, ARMul_State::RecordBreak) is finally taken,
which exposes incorrect logic* in both RecordBreak and ServeBreak.

* a blank BreakpointAddress structure is passed, which sets r15 (PC) to NULL

* gdbstub: DynCom: default-initialize two members/vars used in conditionals

* gdbstub: DynCom: don't record memory watchpoint hits via RecordBreak()

For now, instead check for GDBStub::IsMemoryBreak() in InterpreterMainLoop and ServeBreak.

Fixes PC being set to a stale/unhit breakpoint address (often zero) when a memory watchpoint (rwatch, watch, awatch) is handled in ServeBreak() and generates a GDB trap.

Reasons for removing a call to RecordBreak() for memory watchpoints:
* The``breakpoint_data`` we pass is typed Execute or None. It describes the predicted next code breakpoint hit relative to PC;

* GDBStub::IsMemoryBreak() returns true if a recent Read/Write operation hit a watchpoint. It doesn't specify which in return, nor does it trace it anywhere. Thus, the only data we could give RecordBreak() is a placeholder BreakpointAddress at offset NULL and type Access. I found the idea silly, compared to simply relying on GDBStub::IsMemoryBreak().

There is currently no measure in the code that remembers the addresses (and types) of any watchpoints that were hit by an instruction, in order to send them to GDB as "extended stop information."
I'm considering an implementation for this.

* gdbstub: Change an ASSERT to DEBUG_ASSERT

I have never seen the (Reg[15] == last_bkpt.address) assert fail in practice, even after several weeks of (locally) developping various branches around GDB.  Only leave it inside Debug builds.
2019-03-15 16:31:06 +01:00
Fernando Sahmkow
a8d4927e29 Corrections, documenting and fixes. 2019-02-16 16:52:24 -04:00
Fernando Sahmkow
ecccfe0337 Use u128 on Clock Cycles calculation. 2019-02-15 22:57:16 -04:00
Fernando Sahmkow
5b7ec71fb7 Correct CNTPCT to use Clock Cycles instead of Cpu Cycles. 2019-02-15 22:55:29 -04:00
Lioncash
bd983414f6 core_timing: Convert core timing into a class
Gets rid of the largest set of mutable global state within the core.
This also paves a way for eliminating usages of GetInstance() on the
System class as a follow-up.

Note that no behavioral changes have been made, and this simply extracts
the functionality into a class. This also has the benefit of making
dependencies on the core timing functionality explicit within the
relevant interfaces.
2019-02-15 21:50:25 -05:00
Lioncash
48d9d66dc5 core_timing: Rename CoreTiming namespace to Core::Timing
Places all of the timing-related functionality under the existing Core
namespace to keep things consistent, rather than having the timing
utilities sitting in its own completely separate namespace.
2019-02-12 12:42:17 -05:00
Lioncash
039e58a984 arm_interface: Make include path relative for arm_interface.h
Makes it consistent with the rest of the includes.
2018-12-30 20:46:29 -05:00
Lioncash
a17dd30057 arm_interface: Make LogBacktrace() a const member function
This function doesn't modify instance state, so it can be made const.
2018-12-30 20:44:48 -05:00
Lioncash
776ce5d74c arm_interface: Mark variables as const where applicable in LogBacktrace()
Two of these variables have fixed values, so we can make that
immediately obvious from the get-go.
2018-12-30 20:43:17 -05:00
Lioncash
387bffda5e arm_interface: Remove unnecessary semicolon
Namespaces don't require the use of a semicolon. Silences a -Wextra-semi
warning.
2018-12-30 20:41:33 -05:00
bunnei
331c252509
Merge pull request #1847 from ogniK5377/backtrace-break
Print backtrace on svcBreak
2018-12-29 22:58:13 -05:00
David Marcec
22d4e10664 Moved log backtrace to arm_interface.cpp. Added printing of error code to fatal 2018-12-29 12:55:19 +11:00
David Marcec
08d5663cb8 Moved backtrace to ArmInterface 2018-12-19 14:10:51 +11:00
MerryMage
fd2c42bfcd arm_dynarmic: Set CNTFRQ value 2018-12-18 17:28:12 +00:00
David Marcec
5102c91256 Moved backtrace to ArmInterface
Added to both dynarmic and unicorn
2018-12-03 20:13:48 +11:00
Lioncash
aeadbfa790 core: Make the exclusive monitor a unique_ptr instead of a shared_ptr
Like the barrier, this is owned entirely by the System and will always
outlive the encompassing state, so shared ownership semantics aren't
necessary here.
2018-10-15 14:15:50 -04:00
Lioncash
5c0408596f kernel/thread: Use a regular pointer for the owner/current process
There's no real need to use a shared pointer in these cases, and only
makes object management more fragile in terms of how easy it would be to
introduce cycles. Instead, just do the simple thing of using a regular
pointer. Much of this is just a hold-over from citra anyways.

It also doesn't make sense from a behavioral point of view for a
process' thread to prolong the lifetime of the process itself (the
process is supposed to own the thread, not the other way around).
2018-10-10 02:04:55 -04:00
Lioncash
baed7e1fba kernel/thread: Make all instance variables private
Many of the member variables of the thread class aren't even used
outside of the class itself, so there's no need to make those variables
public. This change follows in the steps of the previous changes that
made other kernel types' members private.

The main motivation behind this is that the Thread class will likely
change in the future as emulation becomes more accurate, and letting
random bits of the emulator access data members of the Thread class
directly makes it a pain to shuffle around and/or modify internals.
Having all data members public like this also makes it difficult to
reason about certain bits of behavior without first verifying what parts
of the core actually use them.

Everything being public also generally follows the tendency for changes
to be introduced in completely different translation units that would
otherwise be better introduced as an addition to the Thread class'
public interface.
2018-10-04 00:14:15 -04:00
Lioncash
cf9d6c6f52 kernel/process: Make data member variables private
Makes the public interface consistent in terms of how accesses are done
on a process object. It also makes it slightly nicer to reason about the
logic of the process class, as we don't want to expose everything to
external code.
2018-09-30 02:30:01 -04:00
Lioncash
16145e2f21 arm_interface: Add missing fpsr/tpidr members to the ThreadContext struct
Internally within the kernel, it also includes a member variable for the
floating-point status register, and TPIDR, so we should do the same here to match
it.

While we're at it, also fix up the size of the struct and add a static
assertion to ensure it always stays the correct size.
2018-09-30 02:29:57 -04:00
bunnei
f7b69d61f2
Merge pull request #1395 from lioncash/vm
process/vm_manager: Initial modifications to load NPDM metadata
2018-09-29 10:54:39 -04:00
Lioncash
7fd598636e memory: Dehardcode the use of a 36-bit address space
Given games can also request a 32-bit or 39-bit address space, we
shouldn't be hardcoding the address space range as 36-bit.
2018-09-24 22:15:53 -04:00
Philippe Babin
fb6bc2c495 FPCR register was uninitialized at start up 2018-09-22 21:17:43 -04:00
Lioncash
9b8fc2b689 arm_interface: Replace kernel vm_manager include with a forward declaration
Avoids an unnecessary inclusion and also uncovers three places where
indirect inclusions were relied upon, which allows us to also resolve
those.
2018-09-20 19:35:36 -04:00
MerryMage
ef31487624 arm_dynarmic: Halt when BRK encountered 2018-09-20 19:12:42 +01:00
MerryMage
3b4a158230 arm_dynarmic: Support BKPT instruction 2018-09-19 21:00:38 +01:00
bunnei
c2cf784376
Merge pull request #1344 from lioncash/arm
arm_interface: Remove ARM11-isms from the CPU interface
2018-09-18 14:24:20 -04:00
Lioncash
ead2a4eeb4 arm_dynarmic: Correct ExclusiveWrite128()'s operation
Previously the second half of the value being written would overwrite
the first half. Thankfully this wasn't a bug that was being encountered,
as the function is currently unused.
2018-09-18 03:56:32 -04:00
Lioncash
b51e7e0288 arm_interface: Remove ARM11-isms from the CPU interface
This modifies the CPU interface to more accurately match an
AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods
don't even make sense to keep around for this interface, as Adv Simd is
used, rather than the VFP in the primary execution state. This is
essentially a modernization change that should have occurred from the
get-go.
2018-09-18 03:20:04 -04:00
fearlessTobi
63c2e32e20 Port #4182 from Citra: "Prefix all size_t with std::" 2018-09-15 15:21:06 +02:00
Markus Wick
10bc725944 Update microprofile scopes.
Blame the subsystems which deserve the blame :)

The updated list is not complete, just the ones I've spotted on random sampling the stack trace.
2018-09-04 11:04:26 +02:00
Lioncash
4a587b81b2 core/core: Replace includes with forward declarations where applicable
The follow-up to e2457418da, which
replaces most of the includes in the core header with forward declarations.

This makes it so that if any of the headers the core header was
previously including change, then no one will need to rebuild the bulk
of the core, due to core.h being quite a prevalent inclusion.

This should make turnaround for changes much faster for developers.
2018-08-31 16:30:14 -04:00
Lioncash
43e0d865fa core: Namespace all code in the arm subdirectory under the Core namespace
Gets all of these types and interfaces out of the global namespace.
2018-08-24 21:50:39 -04:00
MerryMage
94329038b6 dynarmic: Update to 550d662
550d662 load_store_exclusive: Define s == t state to be Constraint_NONE
0b69381 A64/translate: Allow for unpredictable behaviour to be defined
6d236d4 system: Implement MRS CNTFRQ_EL0
6cbb6fb A32/testenv: Add missing headers
6729328 externals: Update xbyak to v5.67
1812bd2 Squashed 'externals/xbyak/' changes from 2794cde7..671fc805
9a95802 externals: Document subtrees
714a840 A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants
8cab459 A64: Implement UQADD/UQSUB's scalar variants
18a8151 ir: Add opcodes for unsigned saturating add and subtract
a5660ee x64/reg_alloc: Use type alias for array returned by GetArgumentInfo()
29489b5 ir/value: Use type alias CoprocessorInfo for std::array<u8, 8>
e23ba26 status_register_access: Add support for bits 0 and 1 of mask to MSR
55190bd fuzz_with_unicorn: Split utility functions into fuzz_util
23b049d A32/translate/load_store: Correct detection of writeback
7ec9f15 A32/translate: Add TranslateSingleInstruction
efeecb4 A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode
08d1d19 A32/decoders: Split instruction list into include file
2d929cc tests: Refactor unicorn_emu to allow for A32 unicorn
f672368 microinstruction: Improve assert messages
7ebff50 emit_x64_vector: EmitVectorNarrow16: AVX512 implementation
edce230 emit_x64_vector: EmitVectorNarrow32: prefer pblendw to loading constant
2018-08-16 10:12:20 +01:00
MerryMage
fcc5155601 arm_dynarmic: Remove IsExecuting check from PrepareReschedule
No longer required. HaltExecution is a no-op if it is not currently executing.
2018-08-13 13:59:01 +01:00
Subv
d923766042 CPU/Timing: Use an approximated amortized amount of ticks when advancing timing.
We divide the number of ticks to add by the number of cores (4) to obtain a more or less rough estimate of the actual number of ticks added. This assumes that all 4 cores are doing similar work. Previously we were adding ~4 times the number of ticks, thus making the games think that time was going way too fast.

This lets us bypass certain hangs in some games like Breath of the Wild.

We should modify our CoreTiming to support multiple cores (both running in a single thread, and in multiple host threads).
2018-08-12 20:41:28 -05:00