flodavid/suyu
1
0
Fork 0
forked from suyu/suyu
Code Pull requests Activity

GPU: Implemented the iadd32i shader instruction.

Browse source
This commit is contained in:
Subv 2018-06-12 11:24:10 -05:00
parent 09b8a16414
commit db0497b808
2 changed files with 31 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/video_core/engines/shader_bytecode.h
View file

@ -217,7 +217,7 @@ union Instruction {
union { union {
BitField<20, 19, u64> imm20_19; BitField<20, 19, u64> imm20_19;
BitField<20, 32, u64> imm20_32; BitField<20, 32, s64> imm20_32;
BitField<45, 1, u64> negate_b; BitField<45, 1, u64> negate_b;
BitField<46, 1, u64> abs_a; BitField<46, 1, u64> abs_a;
BitField<48, 1, u64> negate_a; BitField<48, 1, u64> negate_a;
@ -247,7 +247,7 @@ union Instruction {
float GetImm20_32() const { float GetImm20_32() const {
float result{}; float result{};
u32 imm{static_cast<u32>(imm20_32)}; s32 imm{static_cast<s32>(imm20_32)};
std::memcpy(&result, &imm, sizeof(imm)); std::memcpy(&result, &imm, sizeof(imm));
return result; return result;
} }
@ -270,6 +270,11 @@ union Instruction {
BitField<49, 1, u64> negate_a; BitField<49, 1, u64> negate_a;
} alu_integer; } alu_integer;
union {
BitField<54, 1, u64> saturate;
BitField<56, 1, u64> negate_a;
} iadd32i;
union { union {
BitField<20, 8, u64> shift_position; BitField<20, 8, u64> shift_position;
BitField<28, 8, u64> shift_length; BitField<28, 8, u64> shift_length;
@ -451,6 +456,7 @@ public:
IADD_C, IADD_C,
IADD_R, IADD_R,
IADD_IMM, IADD_IMM,
IADD32I,
ISCADD_C, // Scale and Add ISCADD_C, // Scale and Add
ISCADD_R, ISCADD_R,
ISCADD_IMM, ISCADD_IMM,
@ -510,6 +516,7 @@ public:
Trivial, Trivial,
Arithmetic, Arithmetic,
ArithmeticInteger, ArithmeticInteger,
ArithmeticIntegerImmediate,
Bfe, Bfe,
Logic, Logic,
Shift, Shift,
@ -642,6 +649,7 @@ private:
INST("0100110000010---", Id::IADD_C, Type::ArithmeticInteger, "IADD_C"), INST("0100110000010---", Id::IADD_C, Type::ArithmeticInteger, "IADD_C"),
INST("0101110000010---", Id::IADD_R, Type::ArithmeticInteger, "IADD_R"), INST("0101110000010---", Id::IADD_R, Type::ArithmeticInteger, "IADD_R"),
INST("0011100-00010---", Id::IADD_IMM, Type::ArithmeticInteger, "IADD_IMM"), INST("0011100-00010---", Id::IADD_IMM, Type::ArithmeticInteger, "IADD_IMM"),
INST("0001110---------", Id::IADD32I, Type::ArithmeticIntegerImmediate, "IADD32I"),
INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"), INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"),
INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"), INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"),
INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"), INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"),

21
src/video_core/renderer_opengl/gl_shader_decompiler.cpp
View file

@ -1005,6 +1005,27 @@ private:
break; break;
} }
case OpCode::Type::ArithmeticIntegerImmediate: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
if (instr.iadd32i.negate_a)
op_a = '-' + op_a;
std::string op_b = '(' + std::to_string(instr.alu.imm20_32.Value()) + ')';
switch (opcode->GetId()) {
case OpCode::Id::IADD32I:
regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1,
instr.iadd32i.saturate != 0);
break;
default: {
NGLOG_CRITICAL(HW_GPU, "Unhandled ArithmeticIntegerImmediate instruction: {}",
opcode->GetName());
UNREACHABLE();
}
}
break;
}
case OpCode::Type::ArithmeticInteger: { case OpCode::Type::ArithmeticInteger: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8); std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);