Merge pull request #9535 from bylaws/master
Port over several shader-compiler fixes from skyline
This commit is contained in:
commit
8b251fc3f6
17 changed files with 196 additions and 92 deletions
2
externals/sirit
vendored
2
externals/sirit
vendored
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@ -1 +1 @@
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Subproject commit d7ad93a88864bda94e282e95028f90b5784e4d20
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Subproject commit ab75463999f4f3291976b079d42d52ee91eebf3f
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@ -321,8 +321,12 @@ Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, Id vertex) {
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case IR::Attribute::PositionY:
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case IR::Attribute::PositionY:
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case IR::Attribute::PositionZ:
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case IR::Attribute::PositionZ:
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case IR::Attribute::PositionW:
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case IR::Attribute::PositionW:
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return ctx.OpLoad(ctx.F32[1], AttrPointer(ctx, ctx.input_f32, vertex, ctx.input_position,
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return ctx.OpLoad(
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ctx.Const(element)));
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ctx.F32[1],
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ctx.need_input_position_indirect
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? AttrPointer(ctx, ctx.input_f32, vertex, ctx.input_position, ctx.u32_zero_value,
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ctx.Const(element))
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: AttrPointer(ctx, ctx.input_f32, vertex, ctx.input_position, ctx.Const(element)));
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case IR::Attribute::InstanceId:
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case IR::Attribute::InstanceId:
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if (ctx.profile.support_vertex_instance_id) {
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if (ctx.profile.support_vertex_instance_id) {
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.instance_id));
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.instance_id));
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@ -58,11 +58,10 @@ Id SelectValue(EmitContext& ctx, Id in_range, Id value, Id src_thread_id) {
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ctx.OpGroupNonUniformShuffle(ctx.U32[1], SubgroupScope(ctx), value, src_thread_id), value);
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ctx.OpGroupNonUniformShuffle(ctx.U32[1], SubgroupScope(ctx), value, src_thread_id), value);
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}
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}
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Id GetUpperClamp(EmitContext& ctx, Id invocation_id, Id clamp) {
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Id AddPartitionBase(EmitContext& ctx, Id thread_id) {
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const Id thirty_two{ctx.Const(32u)};
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const Id partition_idx{ctx.OpShiftRightLogical(ctx.U32[1], GetThreadId(ctx), ctx.Const(5u))};
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const Id is_upper_partition{ctx.OpSGreaterThanEqual(ctx.U1, invocation_id, thirty_two)};
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const Id partition_base{ctx.OpShiftLeftLogical(ctx.U32[1], partition_idx, ctx.Const(5u))};
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const Id upper_clamp{ctx.OpIAdd(ctx.U32[1], thirty_two, clamp)};
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return ctx.OpIAdd(ctx.U32[1], thread_id, partition_base);
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return ctx.OpSelect(ctx.U32[1], is_upper_partition, upper_clamp, clamp);
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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@ -145,64 +144,63 @@ Id EmitSubgroupGeMask(EmitContext& ctx) {
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Id EmitShuffleIndex(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id EmitShuffleIndex(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id segmentation_mask) {
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Id segmentation_mask) {
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const Id not_seg_mask{ctx.OpNot(ctx.U32[1], segmentation_mask)};
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const Id not_seg_mask{ctx.OpNot(ctx.U32[1], segmentation_mask)};
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const Id thread_id{GetThreadId(ctx)};
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const Id thread_id{EmitLaneId(ctx)};
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if (ctx.profile.warp_size_potentially_larger_than_guest) {
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const Id thirty_two{ctx.Const(32u)};
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const Id is_upper_partition{ctx.OpSGreaterThanEqual(ctx.U1, thread_id, thirty_two)};
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const Id upper_index{ctx.OpIAdd(ctx.U32[1], thirty_two, index)};
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const Id upper_clamp{ctx.OpIAdd(ctx.U32[1], thirty_two, clamp)};
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index = ctx.OpSelect(ctx.U32[1], is_upper_partition, upper_index, index);
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clamp = ctx.OpSelect(ctx.U32[1], is_upper_partition, upper_clamp, clamp);
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}
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const Id min_thread_id{ComputeMinThreadId(ctx, thread_id, segmentation_mask)};
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const Id min_thread_id{ComputeMinThreadId(ctx, thread_id, segmentation_mask)};
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const Id max_thread_id{ComputeMaxThreadId(ctx, min_thread_id, clamp, not_seg_mask)};
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const Id max_thread_id{ComputeMaxThreadId(ctx, min_thread_id, clamp, not_seg_mask)};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], index, not_seg_mask)};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], index, not_seg_mask)};
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const Id src_thread_id{ctx.OpBitwiseOr(ctx.U32[1], lhs, min_thread_id)};
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Id src_thread_id{ctx.OpBitwiseOr(ctx.U32[1], lhs, min_thread_id)};
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const Id in_range{ctx.OpSLessThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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const Id in_range{ctx.OpSLessThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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if (ctx.profile.warp_size_potentially_larger_than_guest) {
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src_thread_id = AddPartitionBase(ctx, src_thread_id);
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}
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SetInBoundsFlag(inst, in_range);
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SetInBoundsFlag(inst, in_range);
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return SelectValue(ctx, in_range, value, src_thread_id);
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return SelectValue(ctx, in_range, value, src_thread_id);
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}
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}
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Id EmitShuffleUp(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id EmitShuffleUp(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id segmentation_mask) {
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Id segmentation_mask) {
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const Id thread_id{GetThreadId(ctx)};
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const Id thread_id{EmitLaneId(ctx)};
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if (ctx.profile.warp_size_potentially_larger_than_guest) {
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clamp = GetUpperClamp(ctx, thread_id, clamp);
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}
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const Id max_thread_id{GetMaxThreadId(ctx, thread_id, clamp, segmentation_mask)};
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const Id max_thread_id{GetMaxThreadId(ctx, thread_id, clamp, segmentation_mask)};
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const Id src_thread_id{ctx.OpISub(ctx.U32[1], thread_id, index)};
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Id src_thread_id{ctx.OpISub(ctx.U32[1], thread_id, index)};
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const Id in_range{ctx.OpSGreaterThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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const Id in_range{ctx.OpSGreaterThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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if (ctx.profile.warp_size_potentially_larger_than_guest) {
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src_thread_id = AddPartitionBase(ctx, src_thread_id);
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}
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SetInBoundsFlag(inst, in_range);
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SetInBoundsFlag(inst, in_range);
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return SelectValue(ctx, in_range, value, src_thread_id);
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return SelectValue(ctx, in_range, value, src_thread_id);
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}
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}
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Id EmitShuffleDown(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id EmitShuffleDown(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id segmentation_mask) {
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Id segmentation_mask) {
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const Id thread_id{GetThreadId(ctx)};
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const Id thread_id{EmitLaneId(ctx)};
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if (ctx.profile.warp_size_potentially_larger_than_guest) {
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clamp = GetUpperClamp(ctx, thread_id, clamp);
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}
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const Id max_thread_id{GetMaxThreadId(ctx, thread_id, clamp, segmentation_mask)};
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const Id max_thread_id{GetMaxThreadId(ctx, thread_id, clamp, segmentation_mask)};
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const Id src_thread_id{ctx.OpIAdd(ctx.U32[1], thread_id, index)};
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Id src_thread_id{ctx.OpIAdd(ctx.U32[1], thread_id, index)};
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const Id in_range{ctx.OpSLessThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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const Id in_range{ctx.OpSLessThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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if (ctx.profile.warp_size_potentially_larger_than_guest) {
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src_thread_id = AddPartitionBase(ctx, src_thread_id);
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}
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SetInBoundsFlag(inst, in_range);
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SetInBoundsFlag(inst, in_range);
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return SelectValue(ctx, in_range, value, src_thread_id);
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return SelectValue(ctx, in_range, value, src_thread_id);
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}
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}
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Id EmitShuffleButterfly(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id EmitShuffleButterfly(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id segmentation_mask) {
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Id segmentation_mask) {
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const Id thread_id{GetThreadId(ctx)};
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const Id thread_id{EmitLaneId(ctx)};
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if (ctx.profile.warp_size_potentially_larger_than_guest) {
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clamp = GetUpperClamp(ctx, thread_id, clamp);
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}
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const Id max_thread_id{GetMaxThreadId(ctx, thread_id, clamp, segmentation_mask)};
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const Id max_thread_id{GetMaxThreadId(ctx, thread_id, clamp, segmentation_mask)};
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const Id src_thread_id{ctx.OpBitwiseXor(ctx.U32[1], thread_id, index)};
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Id src_thread_id{ctx.OpBitwiseXor(ctx.U32[1], thread_id, index)};
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const Id in_range{ctx.OpSLessThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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const Id in_range{ctx.OpSLessThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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if (ctx.profile.warp_size_potentially_larger_than_guest) {
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src_thread_id = AddPartitionBase(ctx, src_thread_id);
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}
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SetInBoundsFlag(inst, in_range);
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SetInBoundsFlag(inst, in_range);
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return SelectValue(ctx, in_range, value, src_thread_id);
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return SelectValue(ctx, in_range, value, src_thread_id);
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}
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}
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@ -544,7 +544,7 @@ void EmitContext::DefineCommonTypes(const Info& info) {
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U16 = Name(TypeInt(16, false), "u16");
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U16 = Name(TypeInt(16, false), "u16");
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S16 = Name(TypeInt(16, true), "s16");
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S16 = Name(TypeInt(16, true), "s16");
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}
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}
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if (info.uses_int64) {
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if (info.uses_int64 && profile.support_int64) {
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AddCapability(spv::Capability::Int64);
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AddCapability(spv::Capability::Int64);
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U64 = Name(TypeInt(64, false), "u64");
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U64 = Name(TypeInt(64, false), "u64");
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}
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}
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@ -721,9 +721,21 @@ void EmitContext::DefineAttributeMemAccess(const Info& info) {
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size_t label_index{0};
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size_t label_index{0};
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if (info.loads.AnyComponent(IR::Attribute::PositionX)) {
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if (info.loads.AnyComponent(IR::Attribute::PositionX)) {
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AddLabel(labels[label_index]);
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AddLabel(labels[label_index]);
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const Id pointer{is_array
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const Id pointer{[&]() {
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? OpAccessChain(input_f32, input_position, vertex, masked_index)
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if (need_input_position_indirect) {
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: OpAccessChain(input_f32, input_position, masked_index)};
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if (is_array)
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return OpAccessChain(input_f32, input_position, vertex, u32_zero_value,
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masked_index);
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else
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return OpAccessChain(input_f32, input_position, u32_zero_value,
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masked_index);
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} else {
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if (is_array)
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return OpAccessChain(input_f32, input_position, vertex, masked_index);
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else
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return OpAccessChain(input_f32, input_position, masked_index);
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}
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}()};
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const Id result{OpLoad(F32[1], pointer)};
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const Id result{OpLoad(F32[1], pointer)};
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OpReturnValue(result);
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OpReturnValue(result);
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++label_index;
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++label_index;
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@ -1367,15 +1379,28 @@ void EmitContext::DefineInputs(const IR::Program& program) {
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Decorate(layer, spv::Decoration::Flat);
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Decorate(layer, spv::Decoration::Flat);
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}
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}
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if (loads.AnyComponent(IR::Attribute::PositionX)) {
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if (loads.AnyComponent(IR::Attribute::PositionX)) {
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const bool is_fragment{stage != Stage::Fragment};
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const bool is_fragment{stage == Stage::Fragment};
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const spv::BuiltIn built_in{is_fragment ? spv::BuiltIn::Position : spv::BuiltIn::FragCoord};
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if (!is_fragment && profile.has_broken_spirv_position_input) {
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need_input_position_indirect = true;
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const Id input_position_struct = TypeStruct(F32[4]);
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input_position = DefineInput(*this, input_position_struct, true);
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MemberDecorate(input_position_struct, 0, spv::Decoration::BuiltIn,
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static_cast<unsigned>(spv::BuiltIn::Position));
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Decorate(input_position_struct, spv::Decoration::Block);
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} else {
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const spv::BuiltIn built_in{is_fragment ? spv::BuiltIn::FragCoord
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: spv::BuiltIn::Position};
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input_position = DefineInput(*this, F32[4], true, built_in);
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input_position = DefineInput(*this, F32[4], true, built_in);
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if (profile.support_geometry_shader_passthrough) {
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if (profile.support_geometry_shader_passthrough) {
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if (info.passthrough.AnyComponent(IR::Attribute::PositionX)) {
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if (info.passthrough.AnyComponent(IR::Attribute::PositionX)) {
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Decorate(input_position, spv::Decoration::PassthroughNV);
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Decorate(input_position, spv::Decoration::PassthroughNV);
|
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}
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}
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}
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}
|
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}
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}
|
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}
|
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if (loads[IR::Attribute::InstanceId]) {
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if (loads[IR::Attribute::InstanceId]) {
|
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if (profile.support_vertex_instance_id) {
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if (profile.support_vertex_instance_id) {
|
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instance_id = DefineInput(*this, U32[1], true, spv::BuiltIn::InstanceId);
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instance_id = DefineInput(*this, U32[1], true, spv::BuiltIn::InstanceId);
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@ -280,6 +280,7 @@ public:
|
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Id write_global_func_u32x2{};
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Id write_global_func_u32x2{};
|
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Id write_global_func_u32x4{};
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Id write_global_func_u32x4{};
|
||||||
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|
||||||
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bool need_input_position_indirect{};
|
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Id input_position{};
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Id input_position{};
|
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std::array<Id, 32> input_generics{};
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std::array<Id, 32> input_generics{};
|
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|
|
||||||
|
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@ -171,6 +171,70 @@ std::map<IR::Attribute, IR::Attribute> GenerateLegacyToGenericMappings(
|
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}
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}
|
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return mapping;
|
return mapping;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void EmitGeometryPassthrough(IR::IREmitter& ir, const IR::Program& program,
|
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|
const Shader::VaryingState& passthrough_mask,
|
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|
bool passthrough_position,
|
||||||
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std::optional<IR::Attribute> passthrough_layer_attr) {
|
||||||
|
for (u32 i = 0; i < program.output_vertices; i++) {
|
||||||
|
// Assign generics from input
|
||||||
|
for (u32 j = 0; j < 32; j++) {
|
||||||
|
if (!passthrough_mask.Generic(j)) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
const IR::Attribute attr = IR::Attribute::Generic0X + (j * 4);
|
||||||
|
ir.SetAttribute(attr + 0, ir.GetAttribute(attr + 0, ir.Imm32(i)), ir.Imm32(0));
|
||||||
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ir.SetAttribute(attr + 1, ir.GetAttribute(attr + 1, ir.Imm32(i)), ir.Imm32(0));
|
||||||
|
ir.SetAttribute(attr + 2, ir.GetAttribute(attr + 2, ir.Imm32(i)), ir.Imm32(0));
|
||||||
|
ir.SetAttribute(attr + 3, ir.GetAttribute(attr + 3, ir.Imm32(i)), ir.Imm32(0));
|
||||||
|
}
|
||||||
|
|
||||||
|
if (passthrough_position) {
|
||||||
|
// Assign position from input
|
||||||
|
const IR::Attribute attr = IR::Attribute::PositionX;
|
||||||
|
ir.SetAttribute(attr + 0, ir.GetAttribute(attr + 0, ir.Imm32(i)), ir.Imm32(0));
|
||||||
|
ir.SetAttribute(attr + 1, ir.GetAttribute(attr + 1, ir.Imm32(i)), ir.Imm32(0));
|
||||||
|
ir.SetAttribute(attr + 2, ir.GetAttribute(attr + 2, ir.Imm32(i)), ir.Imm32(0));
|
||||||
|
ir.SetAttribute(attr + 3, ir.GetAttribute(attr + 3, ir.Imm32(i)), ir.Imm32(0));
|
||||||
|
}
|
||||||
|
|
||||||
|
if (passthrough_layer_attr) {
|
||||||
|
// Assign layer
|
||||||
|
ir.SetAttribute(IR::Attribute::Layer, ir.GetAttribute(*passthrough_layer_attr),
|
||||||
|
ir.Imm32(0));
|
||||||
|
}
|
||||||
|
|
||||||
|
// Emit vertex
|
||||||
|
ir.EmitVertex(ir.Imm32(0));
|
||||||
|
}
|
||||||
|
ir.EndPrimitive(ir.Imm32(0));
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 GetOutputTopologyVertices(OutputTopology output_topology) {
|
||||||
|
switch (output_topology) {
|
||||||
|
case OutputTopology::PointList:
|
||||||
|
return 1;
|
||||||
|
case OutputTopology::LineStrip:
|
||||||
|
return 2;
|
||||||
|
default:
|
||||||
|
return 3;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void LowerGeometryPassthrough(const IR::Program& program, const HostTranslateInfo& host_info) {
|
||||||
|
for (IR::Block* const block : program.blocks) {
|
||||||
|
for (IR::Inst& inst : block->Instructions()) {
|
||||||
|
if (inst.GetOpcode() == IR::Opcode::Epilogue) {
|
||||||
|
IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
|
||||||
|
EmitGeometryPassthrough(
|
||||||
|
ir, program, program.info.passthrough,
|
||||||
|
program.info.passthrough.AnyComponent(IR::Attribute::PositionX), {});
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
} // Anonymous namespace
|
} // Anonymous namespace
|
||||||
|
|
||||||
IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
|
IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
|
||||||
|
@ -198,6 +262,11 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
|
||||||
for (size_t i = 0; i < program.info.passthrough.mask.size(); ++i) {
|
for (size_t i = 0; i < program.info.passthrough.mask.size(); ++i) {
|
||||||
program.info.passthrough.mask[i] = ((mask[i / 32] >> (i % 32)) & 1) == 0;
|
program.info.passthrough.mask[i] = ((mask[i / 32] >> (i % 32)) & 1) == 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (!host_info.support_geometry_shader_passthrough) {
|
||||||
|
program.output_vertices = GetOutputTopologyVertices(program.output_topology);
|
||||||
|
LowerGeometryPassthrough(program, host_info);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -223,7 +292,7 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
|
||||||
|
|
||||||
Optimization::PositionPass(env, program);
|
Optimization::PositionPass(env, program);
|
||||||
|
|
||||||
Optimization::GlobalMemoryToStorageBufferPass(program);
|
Optimization::GlobalMemoryToStorageBufferPass(program, host_info);
|
||||||
Optimization::TexturePass(env, program, host_info);
|
Optimization::TexturePass(env, program, host_info);
|
||||||
|
|
||||||
if (Settings::values.resolution_info.active) {
|
if (Settings::values.resolution_info.active) {
|
||||||
|
@ -342,17 +411,7 @@ IR::Program GenerateGeometryPassthrough(ObjectPool<IR::Inst>& inst_pool,
|
||||||
IR::Program program;
|
IR::Program program;
|
||||||
program.stage = Stage::Geometry;
|
program.stage = Stage::Geometry;
|
||||||
program.output_topology = output_topology;
|
program.output_topology = output_topology;
|
||||||
switch (output_topology) {
|
program.output_vertices = GetOutputTopologyVertices(output_topology);
|
||||||
case OutputTopology::PointList:
|
|
||||||
program.output_vertices = 1;
|
|
||||||
break;
|
|
||||||
case OutputTopology::LineStrip:
|
|
||||||
program.output_vertices = 2;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
program.output_vertices = 3;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
program.is_geometry_passthrough = false;
|
program.is_geometry_passthrough = false;
|
||||||
program.info.loads.mask = source_program.info.stores.mask;
|
program.info.loads.mask = source_program.info.stores.mask;
|
||||||
|
@ -366,35 +425,8 @@ IR::Program GenerateGeometryPassthrough(ObjectPool<IR::Inst>& inst_pool,
|
||||||
node.data.block = current_block;
|
node.data.block = current_block;
|
||||||
|
|
||||||
IR::IREmitter ir{*current_block};
|
IR::IREmitter ir{*current_block};
|
||||||
for (u32 i = 0; i < program.output_vertices; i++) {
|
EmitGeometryPassthrough(ir, program, program.info.stores, true,
|
||||||
// Assign generics from input
|
source_program.info.emulated_layer);
|
||||||
for (u32 j = 0; j < 32; j++) {
|
|
||||||
if (!program.info.stores.Generic(j)) {
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
const IR::Attribute attr = IR::Attribute::Generic0X + (j * 4);
|
|
||||||
ir.SetAttribute(attr + 0, ir.GetAttribute(attr + 0, ir.Imm32(i)), ir.Imm32(0));
|
|
||||||
ir.SetAttribute(attr + 1, ir.GetAttribute(attr + 1, ir.Imm32(i)), ir.Imm32(0));
|
|
||||||
ir.SetAttribute(attr + 2, ir.GetAttribute(attr + 2, ir.Imm32(i)), ir.Imm32(0));
|
|
||||||
ir.SetAttribute(attr + 3, ir.GetAttribute(attr + 3, ir.Imm32(i)), ir.Imm32(0));
|
|
||||||
}
|
|
||||||
|
|
||||||
// Assign position from input
|
|
||||||
const IR::Attribute attr = IR::Attribute::PositionX;
|
|
||||||
ir.SetAttribute(attr + 0, ir.GetAttribute(attr + 0, ir.Imm32(i)), ir.Imm32(0));
|
|
||||||
ir.SetAttribute(attr + 1, ir.GetAttribute(attr + 1, ir.Imm32(i)), ir.Imm32(0));
|
|
||||||
ir.SetAttribute(attr + 2, ir.GetAttribute(attr + 2, ir.Imm32(i)), ir.Imm32(0));
|
|
||||||
ir.SetAttribute(attr + 3, ir.GetAttribute(attr + 3, ir.Imm32(i)), ir.Imm32(0));
|
|
||||||
|
|
||||||
// Assign layer
|
|
||||||
ir.SetAttribute(IR::Attribute::Layer, ir.GetAttribute(source_program.info.emulated_layer),
|
|
||||||
ir.Imm32(0));
|
|
||||||
|
|
||||||
// Emit vertex
|
|
||||||
ir.EmitVertex(ir.Imm32(0));
|
|
||||||
}
|
|
||||||
ir.EndPrimitive(ir.Imm32(0));
|
|
||||||
|
|
||||||
IR::Block* return_block{block_pool.Create(inst_pool)};
|
IR::Block* return_block{block_pool.Create(inst_pool)};
|
||||||
IR::IREmitter{*return_block}.Epilogue();
|
IR::IREmitter{*return_block}.Epilogue();
|
||||||
|
|
|
@ -15,6 +15,9 @@ struct HostTranslateInfo {
|
||||||
bool needs_demote_reorder{}; ///< True when the device needs DemoteToHelperInvocation reordered
|
bool needs_demote_reorder{}; ///< True when the device needs DemoteToHelperInvocation reordered
|
||||||
bool support_snorm_render_buffer{}; ///< True when the device supports SNORM render buffers
|
bool support_snorm_render_buffer{}; ///< True when the device supports SNORM render buffers
|
||||||
bool support_viewport_index_layer{}; ///< True when the device supports gl_Layer in VS
|
bool support_viewport_index_layer{}; ///< True when the device supports gl_Layer in VS
|
||||||
|
u32 min_ssbo_alignment{}; ///< Minimum alignment supported by the device for SSBOs
|
||||||
|
bool support_geometry_shader_passthrough{}; ///< True when the device supports geometry
|
||||||
|
///< passthrough shaders
|
||||||
};
|
};
|
||||||
|
|
||||||
} // namespace Shader
|
} // namespace Shader
|
||||||
|
|
|
@ -11,6 +11,7 @@
|
||||||
#include "shader_recompiler/frontend/ir/breadth_first_search.h"
|
#include "shader_recompiler/frontend/ir/breadth_first_search.h"
|
||||||
#include "shader_recompiler/frontend/ir/ir_emitter.h"
|
#include "shader_recompiler/frontend/ir/ir_emitter.h"
|
||||||
#include "shader_recompiler/frontend/ir/value.h"
|
#include "shader_recompiler/frontend/ir/value.h"
|
||||||
|
#include "shader_recompiler/host_translate_info.h"
|
||||||
#include "shader_recompiler/ir_opt/passes.h"
|
#include "shader_recompiler/ir_opt/passes.h"
|
||||||
|
|
||||||
namespace Shader::Optimization {
|
namespace Shader::Optimization {
|
||||||
|
@ -402,7 +403,7 @@ void CollectStorageBuffers(IR::Block& block, IR::Inst& inst, StorageInfo& info)
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Returns the offset in indices (not bytes) for an equivalent storage instruction
|
/// Returns the offset in indices (not bytes) for an equivalent storage instruction
|
||||||
IR::U32 StorageOffset(IR::Block& block, IR::Inst& inst, StorageBufferAddr buffer) {
|
IR::U32 StorageOffset(IR::Block& block, IR::Inst& inst, StorageBufferAddr buffer, u32 alignment) {
|
||||||
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
|
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
|
||||||
IR::U32 offset;
|
IR::U32 offset;
|
||||||
if (const std::optional<LowAddrInfo> low_addr{TrackLowAddress(&inst)}) {
|
if (const std::optional<LowAddrInfo> low_addr{TrackLowAddress(&inst)}) {
|
||||||
|
@ -415,7 +416,10 @@ IR::U32 StorageOffset(IR::Block& block, IR::Inst& inst, StorageBufferAddr buffer
|
||||||
}
|
}
|
||||||
// Subtract the least significant 32 bits from the guest offset. The result is the storage
|
// Subtract the least significant 32 bits from the guest offset. The result is the storage
|
||||||
// buffer offset in bytes.
|
// buffer offset in bytes.
|
||||||
const IR::U32 low_cbuf{ir.GetCbuf(ir.Imm32(buffer.index), ir.Imm32(buffer.offset))};
|
IR::U32 low_cbuf{ir.GetCbuf(ir.Imm32(buffer.index), ir.Imm32(buffer.offset))};
|
||||||
|
|
||||||
|
// Align the offset base to match the host alignment requirements
|
||||||
|
low_cbuf = ir.BitwiseAnd(low_cbuf, ir.Imm32(~(alignment - 1U)));
|
||||||
return ir.ISub(offset, low_cbuf);
|
return ir.ISub(offset, low_cbuf);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -510,7 +514,7 @@ void Replace(IR::Block& block, IR::Inst& inst, const IR::U32& storage_index,
|
||||||
}
|
}
|
||||||
} // Anonymous namespace
|
} // Anonymous namespace
|
||||||
|
|
||||||
void GlobalMemoryToStorageBufferPass(IR::Program& program) {
|
void GlobalMemoryToStorageBufferPass(IR::Program& program, const HostTranslateInfo& host_info) {
|
||||||
StorageInfo info;
|
StorageInfo info;
|
||||||
for (IR::Block* const block : program.post_order_blocks) {
|
for (IR::Block* const block : program.post_order_blocks) {
|
||||||
for (IR::Inst& inst : block->Instructions()) {
|
for (IR::Inst& inst : block->Instructions()) {
|
||||||
|
@ -534,7 +538,8 @@ void GlobalMemoryToStorageBufferPass(IR::Program& program) {
|
||||||
const IR::U32 index{IR::Value{static_cast<u32>(info.set.index_of(it))}};
|
const IR::U32 index{IR::Value{static_cast<u32>(info.set.index_of(it))}};
|
||||||
IR::Block* const block{storage_inst.block};
|
IR::Block* const block{storage_inst.block};
|
||||||
IR::Inst* const inst{storage_inst.inst};
|
IR::Inst* const inst{storage_inst.inst};
|
||||||
const IR::U32 offset{StorageOffset(*block, *inst, storage_buffer)};
|
const IR::U32 offset{
|
||||||
|
StorageOffset(*block, *inst, storage_buffer, host_info.min_ssbo_alignment)};
|
||||||
Replace(*block, *inst, index, offset);
|
Replace(*block, *inst, index, offset);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -15,7 +15,7 @@ namespace Shader::Optimization {
|
||||||
void CollectShaderInfoPass(Environment& env, IR::Program& program);
|
void CollectShaderInfoPass(Environment& env, IR::Program& program);
|
||||||
void ConstantPropagationPass(Environment& env, IR::Program& program);
|
void ConstantPropagationPass(Environment& env, IR::Program& program);
|
||||||
void DeadCodeEliminationPass(IR::Program& program);
|
void DeadCodeEliminationPass(IR::Program& program);
|
||||||
void GlobalMemoryToStorageBufferPass(IR::Program& program);
|
void GlobalMemoryToStorageBufferPass(IR::Program& program, const HostTranslateInfo& host_info);
|
||||||
void IdentityRemovalPass(IR::Program& program);
|
void IdentityRemovalPass(IR::Program& program);
|
||||||
void LowerFp16ToFp32(IR::Program& program);
|
void LowerFp16ToFp32(IR::Program& program);
|
||||||
void LowerInt64ToInt32(IR::Program& program);
|
void LowerInt64ToInt32(IR::Program& program);
|
||||||
|
|
|
@ -55,6 +55,8 @@ struct Profile {
|
||||||
|
|
||||||
/// OpFClamp is broken and OpFMax + OpFMin should be used instead
|
/// OpFClamp is broken and OpFMax + OpFMin should be used instead
|
||||||
bool has_broken_spirv_clamp{};
|
bool has_broken_spirv_clamp{};
|
||||||
|
/// The Position builtin needs to be wrapped in a struct when used as an input
|
||||||
|
bool has_broken_spirv_position_input{};
|
||||||
/// Offset image operands with an unsigned type do not work
|
/// Offset image operands with an unsigned type do not work
|
||||||
bool has_broken_unsigned_image_offsets{};
|
bool has_broken_unsigned_image_offsets{};
|
||||||
/// Signed instructions with unsigned data types are misinterpreted
|
/// Signed instructions with unsigned data types are misinterpreted
|
||||||
|
|
|
@ -65,6 +65,8 @@ enum class Interpolation {
|
||||||
struct ConstantBufferDescriptor {
|
struct ConstantBufferDescriptor {
|
||||||
u32 index;
|
u32 index;
|
||||||
u32 count;
|
u32 count;
|
||||||
|
|
||||||
|
auto operator<=>(const ConstantBufferDescriptor&) const = default;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct StorageBufferDescriptor {
|
struct StorageBufferDescriptor {
|
||||||
|
@ -72,6 +74,8 @@ struct StorageBufferDescriptor {
|
||||||
u32 cbuf_offset;
|
u32 cbuf_offset;
|
||||||
u32 count;
|
u32 count;
|
||||||
bool is_written;
|
bool is_written;
|
||||||
|
|
||||||
|
auto operator<=>(const StorageBufferDescriptor&) const = default;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct TextureBufferDescriptor {
|
struct TextureBufferDescriptor {
|
||||||
|
@ -84,6 +88,8 @@ struct TextureBufferDescriptor {
|
||||||
u32 secondary_shift_left;
|
u32 secondary_shift_left;
|
||||||
u32 count;
|
u32 count;
|
||||||
u32 size_shift;
|
u32 size_shift;
|
||||||
|
|
||||||
|
auto operator<=>(const TextureBufferDescriptor&) const = default;
|
||||||
};
|
};
|
||||||
using TextureBufferDescriptors = boost::container::small_vector<TextureBufferDescriptor, 6>;
|
using TextureBufferDescriptors = boost::container::small_vector<TextureBufferDescriptor, 6>;
|
||||||
|
|
||||||
|
@ -95,6 +101,8 @@ struct ImageBufferDescriptor {
|
||||||
u32 cbuf_offset;
|
u32 cbuf_offset;
|
||||||
u32 count;
|
u32 count;
|
||||||
u32 size_shift;
|
u32 size_shift;
|
||||||
|
|
||||||
|
auto operator<=>(const ImageBufferDescriptor&) const = default;
|
||||||
};
|
};
|
||||||
using ImageBufferDescriptors = boost::container::small_vector<ImageBufferDescriptor, 2>;
|
using ImageBufferDescriptors = boost::container::small_vector<ImageBufferDescriptor, 2>;
|
||||||
|
|
||||||
|
@ -110,6 +118,8 @@ struct TextureDescriptor {
|
||||||
u32 secondary_shift_left;
|
u32 secondary_shift_left;
|
||||||
u32 count;
|
u32 count;
|
||||||
u32 size_shift;
|
u32 size_shift;
|
||||||
|
|
||||||
|
auto operator<=>(const TextureDescriptor&) const = default;
|
||||||
};
|
};
|
||||||
using TextureDescriptors = boost::container::small_vector<TextureDescriptor, 12>;
|
using TextureDescriptors = boost::container::small_vector<TextureDescriptor, 12>;
|
||||||
|
|
||||||
|
@ -122,6 +132,8 @@ struct ImageDescriptor {
|
||||||
u32 cbuf_offset;
|
u32 cbuf_offset;
|
||||||
u32 count;
|
u32 count;
|
||||||
u32 size_shift;
|
u32 size_shift;
|
||||||
|
|
||||||
|
auto operator<=>(const ImageDescriptor&) const = default;
|
||||||
};
|
};
|
||||||
using ImageDescriptors = boost::container::small_vector<ImageDescriptor, 4>;
|
using ImageDescriptors = boost::container::small_vector<ImageDescriptor, 4>;
|
||||||
|
|
||||||
|
|
|
@ -1938,14 +1938,21 @@ typename BufferCache<P>::Binding BufferCache<P>::StorageBufferBinding(GPUVAddr s
|
||||||
bool is_written) const {
|
bool is_written) const {
|
||||||
const GPUVAddr gpu_addr = gpu_memory->Read<u64>(ssbo_addr);
|
const GPUVAddr gpu_addr = gpu_memory->Read<u64>(ssbo_addr);
|
||||||
const u32 size = gpu_memory->Read<u32>(ssbo_addr + 8);
|
const u32 size = gpu_memory->Read<u32>(ssbo_addr + 8);
|
||||||
const std::optional<VAddr> cpu_addr = gpu_memory->GpuToCpuAddress(gpu_addr);
|
const u32 alignment = runtime.GetStorageBufferAlignment();
|
||||||
|
|
||||||
|
const GPUVAddr aligned_gpu_addr = Common::AlignDown(gpu_addr, alignment);
|
||||||
|
const u32 aligned_size =
|
||||||
|
Common::AlignUp(static_cast<u32>(gpu_addr - aligned_gpu_addr) + size, alignment);
|
||||||
|
|
||||||
|
const std::optional<VAddr> cpu_addr = gpu_memory->GpuToCpuAddress(aligned_gpu_addr);
|
||||||
if (!cpu_addr || size == 0) {
|
if (!cpu_addr || size == 0) {
|
||||||
return NULL_BINDING;
|
return NULL_BINDING;
|
||||||
}
|
}
|
||||||
const VAddr cpu_end = Common::AlignUp(*cpu_addr + size, Core::Memory::YUZU_PAGESIZE);
|
|
||||||
|
const VAddr cpu_end = Common::AlignUp(*cpu_addr + aligned_size, Core::Memory::YUZU_PAGESIZE);
|
||||||
const Binding binding{
|
const Binding binding{
|
||||||
.cpu_addr = *cpu_addr,
|
.cpu_addr = *cpu_addr,
|
||||||
.size = is_written ? size : static_cast<u32>(cpu_end - *cpu_addr),
|
.size = is_written ? aligned_size : static_cast<u32>(cpu_end - *cpu_addr),
|
||||||
.buffer_id = BufferId{},
|
.buffer_id = BufferId{},
|
||||||
};
|
};
|
||||||
return binding;
|
return binding;
|
||||||
|
|
|
@ -160,6 +160,10 @@ public:
|
||||||
return device.CanReportMemoryUsage();
|
return device.CanReportMemoryUsage();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
u32 GetStorageBufferAlignment() const {
|
||||||
|
return static_cast<u32>(device.GetShaderStorageBufferAlignment());
|
||||||
|
}
|
||||||
|
|
||||||
private:
|
private:
|
||||||
static constexpr std::array PABO_LUT{
|
static constexpr std::array PABO_LUT{
|
||||||
GL_VERTEX_PROGRAM_PARAMETER_BUFFER_NV, GL_TESS_CONTROL_PROGRAM_PARAMETER_BUFFER_NV,
|
GL_VERTEX_PROGRAM_PARAMETER_BUFFER_NV, GL_TESS_CONTROL_PROGRAM_PARAMETER_BUFFER_NV,
|
||||||
|
|
|
@ -236,6 +236,8 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
|
||||||
.needs_demote_reorder = device.IsAmd(),
|
.needs_demote_reorder = device.IsAmd(),
|
||||||
.support_snorm_render_buffer = false,
|
.support_snorm_render_buffer = false,
|
||||||
.support_viewport_index_layer = device.HasVertexViewportLayer(),
|
.support_viewport_index_layer = device.HasVertexViewportLayer(),
|
||||||
|
.min_ssbo_alignment = static_cast<u32>(device.GetShaderStorageBufferAlignment()),
|
||||||
|
.support_geometry_shader_passthrough = device.HasGeometryShaderPassthrough(),
|
||||||
} {
|
} {
|
||||||
if (use_asynchronous_shaders) {
|
if (use_asynchronous_shaders) {
|
||||||
workers = CreateWorkers();
|
workers = CreateWorkers();
|
||||||
|
|
|
@ -330,6 +330,10 @@ bool BufferCacheRuntime::CanReportMemoryUsage() const {
|
||||||
return device.CanReportMemoryUsage();
|
return device.CanReportMemoryUsage();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
u32 BufferCacheRuntime::GetStorageBufferAlignment() const {
|
||||||
|
return static_cast<u32>(device.GetStorageBufferAlignment());
|
||||||
|
}
|
||||||
|
|
||||||
void BufferCacheRuntime::Finish() {
|
void BufferCacheRuntime::Finish() {
|
||||||
scheduler.Finish();
|
scheduler.Finish();
|
||||||
}
|
}
|
||||||
|
|
|
@ -73,6 +73,8 @@ public:
|
||||||
|
|
||||||
bool CanReportMemoryUsage() const;
|
bool CanReportMemoryUsage() const;
|
||||||
|
|
||||||
|
u32 GetStorageBufferAlignment() const;
|
||||||
|
|
||||||
[[nodiscard]] StagingBufferRef UploadStagingBuffer(size_t size);
|
[[nodiscard]] StagingBufferRef UploadStagingBuffer(size_t size);
|
||||||
|
|
||||||
[[nodiscard]] StagingBufferRef DownloadStagingBuffer(size_t size);
|
[[nodiscard]] StagingBufferRef DownloadStagingBuffer(size_t size);
|
||||||
|
|
|
@ -331,6 +331,7 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
|
||||||
.need_declared_frag_colors = false,
|
.need_declared_frag_colors = false,
|
||||||
|
|
||||||
.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS,
|
.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS,
|
||||||
|
.has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,
|
||||||
.has_broken_unsigned_image_offsets = false,
|
.has_broken_unsigned_image_offsets = false,
|
||||||
.has_broken_signed_operations = false,
|
.has_broken_signed_operations = false,
|
||||||
.has_broken_fp16_float_controls = driver_id == VK_DRIVER_ID_NVIDIA_PROPRIETARY,
|
.has_broken_fp16_float_controls = driver_id == VK_DRIVER_ID_NVIDIA_PROPRIETARY,
|
||||||
|
@ -343,6 +344,8 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
|
||||||
driver_id == VK_DRIVER_ID_AMD_PROPRIETARY || driver_id == VK_DRIVER_ID_AMD_OPEN_SOURCE,
|
driver_id == VK_DRIVER_ID_AMD_PROPRIETARY || driver_id == VK_DRIVER_ID_AMD_OPEN_SOURCE,
|
||||||
.support_snorm_render_buffer = true,
|
.support_snorm_render_buffer = true,
|
||||||
.support_viewport_index_layer = device.IsExtShaderViewportIndexLayerSupported(),
|
.support_viewport_index_layer = device.IsExtShaderViewportIndexLayerSupported(),
|
||||||
|
.min_ssbo_alignment = static_cast<u32>(device.GetStorageBufferAlignment()),
|
||||||
|
.support_geometry_shader_passthrough = device.IsNvGeometryShaderPassthroughSupported(),
|
||||||
};
|
};
|
||||||
|
|
||||||
if (device.GetMaxVertexInputAttributes() < Maxwell::NumVertexAttributes) {
|
if (device.GetMaxVertexInputAttributes() < Maxwell::NumVertexAttributes) {
|
||||||
|
|
Loading…
Reference in a new issue