shader: Address feedback
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cb6fc03e55
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4d0d29fc20
5 changed files with 49 additions and 53 deletions
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@ -72,20 +72,19 @@ public:
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explicit ImageOperands(EmitContext& ctx, bool has_lod_clamp, Id derivates, u32 num_derivates,
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Id offset, Id lod_clamp) {
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if (Sirit::ValidId(derivates)) {
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boost::container::static_vector<Id, 3> deriv_x_accum;
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boost::container::static_vector<Id, 3> deriv_y_accum;
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for (size_t i = 0; i < num_derivates; i++) {
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deriv_x_accum.push_back(ctx.OpCompositeExtract(ctx.F32[1], derivates, i * 2));
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deriv_y_accum.push_back(ctx.OpCompositeExtract(ctx.F32[1], derivates, i * 2 + 1));
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}
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Id derivates_X = ctx.OpCompositeConstruct(
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ctx.F32[num_derivates], std::span{deriv_x_accum.data(), deriv_x_accum.size()});
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Id derivates_Y = ctx.OpCompositeConstruct(
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ctx.F32[num_derivates], std::span{deriv_y_accum.data(), deriv_y_accum.size()});
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Add(spv::ImageOperandsMask::Grad, derivates_X, derivates_Y);
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} else {
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throw LogicError("Derivates must be present");
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}
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boost::container::static_vector<Id, 3> deriv_x_accum;
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boost::container::static_vector<Id, 3> deriv_y_accum;
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for (size_t i = 0; i < num_derivates; i++) {
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deriv_x_accum.push_back(ctx.OpCompositeExtract(ctx.F32[1], derivates, i * 2));
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deriv_y_accum.push_back(ctx.OpCompositeExtract(ctx.F32[1], derivates, i * 2 + 1));
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}
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const Id derivates_X{ctx.OpCompositeConstruct(
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ctx.F32[num_derivates], std::span{deriv_x_accum.data(), deriv_x_accum.size()})};
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const Id derivates_Y{ctx.OpCompositeConstruct(
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ctx.F32[num_derivates], std::span{deriv_y_accum.data(), deriv_y_accum.size()})};
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Add(spv::ImageOperandsMask::Grad, derivates_X, derivates_Y);
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if (Sirit::ValidId(offset)) {
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Add(spv::ImageOperandsMask::Offset, offset);
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}
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@ -100,10 +99,10 @@ public:
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operands.push_back(value);
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}
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void Add(spv::ImageOperandsMask new_mask, Id value, Id value_2) {
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void Add(spv::ImageOperandsMask new_mask, Id value_1, Id value_2) {
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mask = static_cast<spv::ImageOperandsMask>(static_cast<unsigned>(mask) |
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static_cast<unsigned>(new_mask));
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operands.push_back(value);
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operands.push_back(value_1);
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operands.push_back(value_2);
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}
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@ -345,7 +344,8 @@ Id EmitImageQueryLod(EmitContext& ctx, IR::Inst*, const IR::Value& index, Id coo
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Id EmitImageGradient(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
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Id derivates, Id offset, Id lod_clamp) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const ImageOperands operands(ctx, info.has_lod_clamp != 0, derivates, info.num_derivates, offset, lod_clamp);
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const ImageOperands operands(ctx, info.has_lod_clamp != 0, derivates, info.num_derivates,
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offset, lod_clamp);
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return Emit(&EmitContext::OpImageSparseSampleExplicitLod,
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&EmitContext::OpImageSampleExplicitLod, ctx, inst, ctx.F32[4], Texture(ctx, index),
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coords, operands.Mask(), operands.Span());
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@ -47,7 +47,7 @@ Shader::TextureType GetType(TextureType type, bool dc) {
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IR::Value MakeOffset(TranslatorVisitor& v, IR::Reg reg, bool has_lod_clamp) {
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const IR::U32 value{v.X(reg)};
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const u32 base = has_lod_clamp ? 12 : 16;
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const u32 base{has_lod_clamp ? 12U : 16U};
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return v.ir.CompositeConstruct(
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v.ir.BitFieldExtract(value, v.ir.Imm32(base), v.ir.Imm32(4), true),
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v.ir.BitFieldExtract(value, v.ir.Imm32(base + 4), v.ir.Imm32(4), true));
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@ -74,20 +74,21 @@ void Impl(TranslatorVisitor& v, u64 insn, bool is_bindless) {
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}
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IR::Value coords;
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u32 num_derivates;
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IR::Reg base_reg = txd.coord_reg;
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u32 num_derivates{};
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IR::Reg base_reg{txd.coord_reg};
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IR::Reg last_reg;
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IR::Value handle;
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if (!is_bindless) {
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handle = v.ir.Imm32(static_cast<u32>(txd.cbuf_offset.Value() * 4));
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} else {
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if (is_bindless) {
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handle = v.X(base_reg++);
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} else {
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handle = v.ir.Imm32(static_cast<u32>(txd.cbuf_offset.Value() * 4));
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}
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const auto read_array{[&]() -> IR::F32 {
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return v.ir.ConvertUToF(32, 16,
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v.ir.BitFieldExtract(v.X(last_reg), v.ir.Imm32(0),
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v.ir.Imm32(has_lod_clamp ? 12 : 16)));
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const IR::U32 base{v.ir.Imm32(0)};
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const IR::U32 count{v.ir.Imm32(has_lod_clamp ? 12 : 16)};
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const IR::U32 array_index{v.ir.BitFieldExtract(v.X(last_reg), base, count)};
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return v.ir.ConvertUToF(32, 16, array_index);
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}};
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switch (txd.type) {
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case TextureType::_1D: {
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@ -141,19 +142,20 @@ void Impl(TranslatorVisitor& v, u64 insn, bool is_bindless) {
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IR::F32 lod_clamp;
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if (has_lod_clamp) {
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const IR::F32 conv4_8fixp_f = v.ir.Imm32(Common::BitCast<f32>(0x3b800000U));
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const IR::F32 tmp = v.ir.ConvertUToF(
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32, 16, v.ir.BitFieldExtract(v.X(last_reg), v.ir.Imm32(20), v.ir.Imm32(12)));
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lod_clamp = v.ir.FPMul(tmp, conv4_8fixp_f);
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// Lod Clamp is a Fixed Point 4.8, we need to transform it to float.
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// to convert a fixed point, float(value) / float(1 << fixed_point)
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// in this case the fixed_point is 8.
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const IR::F32 conv4_8fixp_f{v.ir.Imm32(static_cast<f32>(1U << 8))};
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const IR::F32 fixp_lc{v.ir.ConvertUToF(
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32, 16, v.ir.BitFieldExtract(v.X(last_reg), v.ir.Imm32(20), v.ir.Imm32(12)))};
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lod_clamp = v.ir.FPMul(fixp_lc, conv4_8fixp_f);
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}
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IR::TextureInstInfo info{};
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info.type.Assign(GetType(txd.type, false));
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info.num_derivates.Assign(num_derivates);
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info.has_lod_clamp.Assign(has_lod_clamp ? 1 : 0);
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const IR::Value sample{[&]() -> IR::Value {
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return v.ir.ImageGradient(handle, coords, derivates, offset, lod_clamp, info);
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}()};
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const IR::Value sample{v.ir.ImageGradient(handle, coords, derivates, offset, lod_clamp, info)};
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IR::Reg dest_reg{txd.dest_reg};
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for (size_t element = 0; element < 4; ++element) {
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@ -117,10 +117,10 @@ void Impl(TranslatorVisitor& v, u64 insn, bool is_bindless) {
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IR::Value offset;
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IR::U32 lod;
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IR::U32 multisample;
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if (!is_bindless) {
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handle = v.ir.Imm32(static_cast<u32>(tld.cbuf_offset.Value() * 4));
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} else {
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if (is_bindless) {
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handle = v.X(meta_reg++);
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} else {
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handle = v.ir.Imm32(static_cast<u32>(tld.cbuf_offset.Value() * 4));
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}
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if (tld.lod != 0) {
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lod = v.X(meta_reg++);
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@ -138,9 +138,7 @@ void Impl(TranslatorVisitor& v, u64 insn, bool is_bindless) {
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}
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IR::TextureInstInfo info{};
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info.type.Assign(GetType(tld.type, false));
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const IR::Value sample{[&]() -> IR::Value {
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return v.ir.ImageFetch(handle, coords, offset, lod, multisample, info);
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}()};
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const IR::Value sample{v.ir.ImageFetch(handle, coords, offset, lod, multisample, info)};
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IR::Reg dest_reg{tld.dest_reg};
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for (size_t element = 0; element < 4; ++element) {
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@ -81,39 +81,35 @@ void Impl(TranslatorVisitor& v, u64 insn, bool is_bindless) {
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BitField<36, 13, u64> cbuf_offset;
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} const tmml{insn};
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if ((tmml.mask & 0xC) != 0) {
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if ((tmml.mask & 0b1100) != 0) {
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throw NotImplementedException("TMML BA results are not implmented");
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}
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IR::F32 transform_constant = v.ir.Imm32(256.0f);
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IR::F32 transform_constant{v.ir.Imm32(256.0f)};
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const IR::Value coords{MakeCoords(v, tmml.coord_reg, tmml.type)};
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IR::U32 handle;
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IR::Reg meta_reg{tmml.meta_reg};
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if (!is_bindless) {
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handle = v.ir.Imm32(static_cast<u32>(tmml.cbuf_offset.Value() * 4));
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} else {
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if (is_bindless) {
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handle = v.X(meta_reg++);
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} else {
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handle = v.ir.Imm32(static_cast<u32>(tmml.cbuf_offset.Value() * 4));
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}
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IR::TextureInstInfo info{};
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info.type.Assign(GetType(tmml.type, false));
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const IR::Value sample{
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[&]() -> IR::Value { return v.ir.ImageQueryLod(handle, coords, info); }()};
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const IR::Value sample{v.ir.ImageQueryLod(handle, coords, info)};
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const IR::FpControl fp_control{
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.no_contraction{false},
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.rounding{IR::FpRounding::RP},
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.fmz_mode{IR::FmzMode::FTZ},
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};
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IR::Reg dest_reg{tmml.dest_reg};
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for (size_t element = 0; element < 4; ++element) {
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if (((tmml.mask >> element) & 1) == 0) {
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continue;
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}
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IR::F32 value = IR::F32{v.ir.CompositeExtract(sample, element)};
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v.F(dest_reg,
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element < 2 ? IR::F32{v.ir.FPMul(value, transform_constant, fp_control)} : value);
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IR::F32 value{v.ir.CompositeExtract(sample, element)};
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if (element < 2) {
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value = v.ir.FPMul(value, transform_constant);
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}
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v.F(dest_reg, value);
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++dest_reg;
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}
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}
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@ -64,7 +64,7 @@ void MemoryManager::Unmap(GPUVAddr gpu_addr, std::size_t size) {
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}
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const auto it = std::ranges::lower_bound(map_ranges, gpu_addr, {}, &MapRange::first);
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if (it != map_ranges.end()) {
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// ASSERT(it->first == gpu_addr);
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ASSERT(it->first == gpu_addr);
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map_ranges.erase(it);
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} else {
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UNREACHABLE_MSG("Unmapping non-existent GPU address=0x{:x}", gpu_addr);
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