diff --git a/src/shader_recompiler/backend/glasm/reg_alloc.cpp b/src/shader_recompiler/backend/glasm/reg_alloc.cpp
index 55e8107e9c..010ad02759 100644
--- a/src/shader_recompiler/backend/glasm/reg_alloc.cpp
+++ b/src/shader_recompiler/backend/glasm/reg_alloc.cpp
@@ -68,11 +68,11 @@ Id RegAlloc::Alloc() {
         }
         num_used_registers = std::max(num_used_registers, reg + 1);
         register_use[reg] = true;
-        return Id{
-            .index = static_cast<u32>(reg),
-            .is_spill = 0,
-            .is_condition_code = 0,
-        };
+        Id ret{};
+        ret.index.Assign(static_cast<u32>(reg));
+        ret.is_spill.Assign(0);
+        ret.is_condition_code.Assign(0);
+        return ret;
     }
     throw NotImplementedException("Register spilling");
 }
diff --git a/src/shader_recompiler/backend/glasm/reg_alloc.h b/src/shader_recompiler/backend/glasm/reg_alloc.h
index 83d728d202..f73aa3348f 100644
--- a/src/shader_recompiler/backend/glasm/reg_alloc.h
+++ b/src/shader_recompiler/backend/glasm/reg_alloc.h
@@ -6,6 +6,7 @@
 
 #include <bitset>
 
+#include "common/bit_field.h"
 #include "common/common_types.h"
 
 namespace Shader::IR {
@@ -18,9 +19,12 @@ namespace Shader::Backend::GLASM {
 class EmitContext;
 
 struct Id {
-    u32 index : 30;
-    u32 is_spill : 1;
-    u32 is_condition_code : 1;
+    union {
+        u32 raw;
+        BitField<0, 30, u32> index;
+        BitField<30, 1, u32> is_spill;
+        BitField<31, 1, u32> is_condition_code;
+    };
 };
 
 class RegAlloc {