maxwell_dma: Minor refactoring
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1ea8073783
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24049591f6
2 changed files with 33 additions and 33 deletions
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@ -82,42 +82,42 @@ void MaxwellDMA::Launch() {
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}
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}
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void MaxwellDMA::CopyPitchToPitch() {
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void MaxwellDMA::CopyPitchToPitch() {
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// When `multi_line_enable` bit is disabled the copy is performed as if we were copying a 1D
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// When `multi_line_enable` bit is enabled we copy a 2D image of dimensions
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// buffer of length `line_length_in`.
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// (line_length_in, line_count).
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// Otherwise we copy a 2D image of dimensions (line_length_in, line_count).
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// Otherwise the copy is performed as if we were copying a 1D buffer of length line_length_in.
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auto& accelerate = rasterizer->AccessAccelerateDMA();
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const bool remap_enabled = regs.launch_dma.remap_enable != 0;
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if (!regs.launch_dma.multi_line_enable) {
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if (regs.launch_dma.multi_line_enable) {
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const bool is_buffer_clear = regs.launch_dma.remap_enable != 0 &&
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UNIMPLEMENTED_IF(remap_enabled);
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regs.remap_const.dst_x == RemapConst::Swizzle::CONST_A;
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// TODO: allow multisized components.
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if (is_buffer_clear) {
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ASSERT(regs.remap_const.component_size_minus_one == 3);
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accelerate.BufferClear(regs.offset_out, regs.line_length_in, regs.remap_consta_value);
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std::vector<u32> tmp_buffer(regs.line_length_in, regs.remap_consta_value);
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memory_manager.WriteBlockUnsafe(regs.offset_out,
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reinterpret_cast<u8*>(tmp_buffer.data()),
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regs.line_length_in * sizeof(u32));
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return;
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}
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UNIMPLEMENTED_IF(regs.launch_dma.remap_enable != 0);
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if (!accelerate.BufferCopy(regs.offset_in, regs.offset_out, regs.line_length_in)) {
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std::vector<u8> tmp_buffer(regs.line_length_in);
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memory_manager.ReadBlockUnsafe(regs.offset_in, tmp_buffer.data(), regs.line_length_in);
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memory_manager.WriteBlock(regs.offset_out, tmp_buffer.data(), regs.line_length_in);
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}
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return;
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}
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UNIMPLEMENTED_IF(regs.launch_dma.remap_enable != 0);
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// Perform a line-by-line copy.
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// Perform a line-by-line copy.
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// We're going to take a subrect of size (line_length_in, line_count) from the source rectangle.
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// We're going to take a subrect of size (line_length_in, line_count) from the source
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// There is no need to manually flush/invalidate the regions because CopyBlock does that for us.
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// rectangle. There is no need to manually flush/invalidate the regions because CopyBlock
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// does that for us.
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for (u32 line = 0; line < regs.line_count; ++line) {
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for (u32 line = 0; line < regs.line_count; ++line) {
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const GPUVAddr source_line = regs.offset_in + static_cast<size_t>(line) * regs.pitch_in;
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const GPUVAddr source_line = regs.offset_in + static_cast<size_t>(line) * regs.pitch_in;
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const GPUVAddr dest_line = regs.offset_out + static_cast<size_t>(line) * regs.pitch_out;
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const GPUVAddr dest_line = regs.offset_out + static_cast<size_t>(line) * regs.pitch_out;
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memory_manager.CopyBlock(dest_line, source_line, regs.line_length_in);
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memory_manager.CopyBlock(dest_line, source_line, regs.line_length_in);
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}
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}
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return;
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}
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// TODO: allow multisized components.
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auto& accelerate = rasterizer->AccessAccelerateDMA();
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const bool is_const_a_dst = regs.remap_const.dst_x == RemapConst::Swizzle::CONST_A;
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const bool is_buffer_clear = remap_enabled && is_const_a_dst;
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if (is_buffer_clear) {
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ASSERT(regs.remap_const.component_size_minus_one == 3);
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accelerate.BufferClear(regs.offset_out, regs.line_length_in, regs.remap_consta_value);
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std::vector<u32> tmp_buffer(regs.line_length_in, regs.remap_consta_value);
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memory_manager.WriteBlockUnsafe(regs.offset_out, reinterpret_cast<u8*>(tmp_buffer.data()),
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regs.line_length_in * sizeof(u32));
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return;
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}
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UNIMPLEMENTED_IF(remap_enabled);
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if (!accelerate.BufferCopy(regs.offset_in, regs.offset_out, regs.line_length_in)) {
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std::vector<u8> tmp_buffer(regs.line_length_in);
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memory_manager.ReadBlockUnsafe(regs.offset_in, tmp_buffer.data(), regs.line_length_in);
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memory_manager.WriteBlock(regs.offset_out, tmp_buffer.data(), regs.line_length_in);
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}
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}
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}
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void MaxwellDMA::CopyBlockLinearToPitch() {
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void MaxwellDMA::CopyBlockLinearToPitch() {
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@ -175,7 +175,7 @@ public:
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static_assert(sizeof(LaunchDMA) == 4);
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static_assert(sizeof(LaunchDMA) == 4);
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struct RemapConst {
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struct RemapConst {
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enum Swizzle : u32 {
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enum class Swizzle : u32 {
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SRC_X = 0,
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SRC_X = 0,
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SRC_Y = 1,
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SRC_Y = 1,
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SRC_Z = 2,
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SRC_Z = 2,
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