forked from suyu/suyu
dyncom: Move over SASX/SSAX/SADD16/SSUB16
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0f696037f6
commit
c6f27055c9
1 changed files with 102 additions and 7 deletions
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@ -1019,6 +1019,15 @@ typedef struct _arm_inst {
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char component[0];
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} arm_inst;
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typedef struct generic_arm_inst {
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u32 Ra;
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u32 Rm;
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u32 Rn;
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u32 Rd;
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u8 op1;
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u8 op2;
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} generic_arm_inst;
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typedef struct _adc_inst {
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unsigned int I;
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unsigned int S;
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@ -2469,9 +2478,29 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index)
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}
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SADD16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SADD8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SADDSUBX"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rn = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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inst_cream->op1 = BITS(inst, 20, 21);
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inst_cream->op2 = BITS(inst, 5, 7);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(sadd16)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sbc_inst));
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@ -2637,9 +2666,15 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) { UNI
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ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSAT"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSAT16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSUB16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSUB8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSUBADDX"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(sadd16)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(sadd16)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(stc)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(stc_inst));
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@ -5626,9 +5661,71 @@ unsigned InterpreterMainLoop(ARMul_State* state)
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SADD16_INST:
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SADD8_INST:
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SADD16_INST:
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SADDSUBX_INST:
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SSUBADDX_INST:
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SSUB16_INST:
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{
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INC_ICOUNTER;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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const s16 rn_lo = (RN & 0xFFFF);
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const s16 rn_hi = ((RN >> 16) & 0xFFFF);
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const s16 rm_lo = (RM & 0xFFFF);
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const s16 rm_hi = ((RM >> 16) & 0xFFFF);
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s32 lo_result = 0;
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s32 hi_result = 0;
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// SADD16
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if (inst_cream->op2 == 0x00) {
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lo_result = (rn_lo + rm_lo);
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hi_result = (rn_hi + rm_hi);
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}
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// SASX
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else if (inst_cream->op2 == 0x01) {
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lo_result = (rn_lo - rm_hi);
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hi_result = (rn_hi + rm_lo);
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}
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// SSAX
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else if (inst_cream->op2 == 0x02) {
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lo_result = (rn_lo + rm_hi);
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hi_result = (rn_hi - rm_lo);
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}
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// SSUB16
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else if (inst_cream->op2 == 0x03) {
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lo_result = (rn_lo - rm_lo);
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hi_result = (rn_hi - rm_hi);
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}
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RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
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if (lo_result >= 0) {
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cpu->Cpsr |= (1 << 16);
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cpu->Cpsr |= (1 << 17);
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} else {
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cpu->Cpsr &= ~(1 << 16);
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cpu->Cpsr &= ~(1 << 17);
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}
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if (hi_result >= 0) {
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cpu->Cpsr |= (1 << 18);
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cpu->Cpsr |= (1 << 19);
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} else {
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cpu->Cpsr &= ~(1 << 18);
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cpu->Cpsr &= ~(1 << 19);
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(generic_arm_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SBC_INST:
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{
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INC_ICOUNTER;
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@ -5851,9 +5948,7 @@ unsigned InterpreterMainLoop(ARMul_State* state)
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SRS_INST:
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SSAT_INST:
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SSAT16_INST:
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SSUB16_INST:
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SSUB8_INST:
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SSUBADDX_INST:
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STC_INST:
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{
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INC_ICOUNTER;
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