forked from suyu/suyu
GPU: Stub the SSY shader instruction.
This instruction tells the GPU where the flow reconverges in a non-uniform control flow scenario, we can ignore this when generating GLSL code.
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2 changed files with 7 additions and 0 deletions
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@ -410,6 +410,7 @@ class OpCode {
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public:
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public:
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enum class Id {
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enum class Id {
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KIL,
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KIL,
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SSY,
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BFE_C,
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BFE_C,
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BFE_R,
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BFE_R,
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BFE_IMM,
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BFE_IMM,
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@ -596,6 +597,7 @@ private:
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std::vector<Matcher> table = {
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std::vector<Matcher> table = {
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#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name)
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#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name)
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("111000101001----", Id::SSY, Type::Flow, "SSY"),
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INST("111000100100----", Id::BRA, Type::Flow, "BRA"),
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INST("111000100100----", Id::BRA, Type::Flow, "BRA"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"),
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INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"),
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@ -1435,6 +1435,11 @@ private:
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regs.SetRegisterToInputAttibute(instr.gpr0, attribute.element, attribute.index);
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regs.SetRegisterToInputAttibute(instr.gpr0, attribute.element, attribute.index);
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break;
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break;
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}
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}
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case OpCode::Id::SSY: {
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// The SSY opcode tells the GPU where to re-converge divergent execution paths, we
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// can ignore this when generating GLSL code.
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break;
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}
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default: {
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default: {
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NGLOG_CRITICAL(HW_GPU, "Unhandled instruction: {}", opcode->GetName());
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NGLOG_CRITICAL(HW_GPU, "Unhandled instruction: {}", opcode->GetName());
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UNREACHABLE();
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UNREACHABLE();
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