16145e2f21
Internally within the kernel, it also includes a member variable for the floating-point status register, and TPIDR, so we should do the same here to match it. While we're at it, also fix up the size of the struct and add a static assertion to ensure it always stays the correct size.
146 lines
3.8 KiB
C++
146 lines
3.8 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include "common/common_types.h"
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namespace Kernel {
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enum class VMAPermission : u8;
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}
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namespace Core {
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/// Generic ARMv8 CPU interface
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class ARM_Interface : NonCopyable {
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public:
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virtual ~ARM_Interface() {}
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struct ThreadContext {
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std::array<u64, 31> cpu_registers;
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u64 sp;
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u64 pc;
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u32 pstate;
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std::array<u8, 4> padding;
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std::array<u128, 32> vector_registers;
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u32 fpcr;
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u32 fpsr;
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u64 tpidr;
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};
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// Internally within the kernel, it expects the AArch64 version of the
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// thread context to be 800 bytes in size.
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static_assert(sizeof(ThreadContext) == 0x320);
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/// Runs the CPU until an event happens
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virtual void Run() = 0;
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/// Step CPU by one instruction
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virtual void Step() = 0;
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/// Maps a backing memory region for the CPU
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virtual void MapBackingMemory(VAddr address, std::size_t size, u8* memory,
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Kernel::VMAPermission perms) = 0;
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/// Unmaps a region of memory that was previously mapped using MapBackingMemory
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virtual void UnmapMemory(VAddr address, std::size_t size) = 0;
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/// Clear all instruction cache
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virtual void ClearInstructionCache() = 0;
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/// Notify CPU emulation that page tables have changed
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virtual void PageTableChanged() = 0;
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/**
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* Set the Program Counter to an address
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* @param addr Address to set PC to
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*/
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virtual void SetPC(u64 addr) = 0;
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/*
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* Get the current Program Counter
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* @return Returns current PC
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*/
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virtual u64 GetPC() const = 0;
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/**
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* Get an ARM register
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* @param index Register index
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* @return Returns the value in the register
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*/
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virtual u64 GetReg(int index) const = 0;
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/**
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* Set an ARM register
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* @param index Register index
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* @param value Value to set register to
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*/
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virtual void SetReg(int index, u64 value) = 0;
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/**
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* Gets the value of a specified vector register.
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*
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* @param index The index of the vector register.
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* @return the value within the vector register.
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*/
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virtual u128 GetVectorReg(int index) const = 0;
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/**
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* Sets a given value into a vector register.
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*
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* @param index The index of the vector register.
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* @param value The new value to place in the register.
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*/
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virtual void SetVectorReg(int index, u128 value) = 0;
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/**
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* Get the current PSTATE register
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* @return Returns the value of the PSTATE register
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*/
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virtual u32 GetPSTATE() const = 0;
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/**
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* Set the current PSTATE register
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* @param pstate Value to set PSTATE to
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*/
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virtual void SetPSTATE(u32 pstate) = 0;
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virtual VAddr GetTlsAddress() const = 0;
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virtual void SetTlsAddress(VAddr address) = 0;
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/**
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* Gets the value within the TPIDR_EL0 (read/write software thread ID) register.
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*
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* @return the value within the register.
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*/
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virtual u64 GetTPIDR_EL0() const = 0;
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/**
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* Sets a new value within the TPIDR_EL0 (read/write software thread ID) register.
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*
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* @param value The new value to place in the register.
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*/
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virtual void SetTPIDR_EL0(u64 value) = 0;
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/**
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* Saves the current CPU context
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* @param ctx Thread context to save
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*/
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virtual void SaveContext(ThreadContext& ctx) = 0;
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/**
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* Loads a CPU context
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* @param ctx Thread context to load
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*/
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virtual void LoadContext(const ThreadContext& ctx) = 0;
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/// Clears the exclusive monitor's state.
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virtual void ClearExclusiveState() = 0;
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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virtual void PrepareReschedule() = 0;
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};
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} // namespace Core
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