Merge pull request #1477 from ReinUsesLisp/vmad
gl_shader_decompiler: Implement VMAD
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bunnei
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2 changed files with 118 additions and 0 deletions
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@ -214,6 +214,18 @@ enum class IMinMaxExchange : u64 {
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XHi = 3,
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};
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enum class VmadType : u64 {
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Size16_Low = 0,
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Size16_High = 1,
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Size32 = 2,
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Invalid = 3,
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};
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enum class VmadShr : u64 {
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Shr7 = 1,
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Shr15 = 2,
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};
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enum class XmadMode : u64 {
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None = 0,
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CLo = 1,
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@ -452,6 +464,7 @@ union Instruction {
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BitField<48, 16, u64> opcode;
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union {
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BitField<20, 16, u64> imm20_16;
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BitField<20, 19, u64> imm20_19;
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BitField<20, 32, s64> imm20_32;
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BitField<45, 1, u64> negate_b;
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@ -493,6 +506,10 @@ union Instruction {
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}
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} lop3;
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u16 GetImm20_16() const {
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return static_cast<u16>(imm20_16);
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}
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u32 GetImm20_19() const {
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u32 imm{static_cast<u32>(imm20_19)};
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imm <<= 12;
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@ -1016,6 +1033,23 @@ union Instruction {
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BitField<47, 2, IsberdShift> shift;
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} isberd;
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union {
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BitField<48, 1, u64> signed_a;
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BitField<38, 1, u64> is_byte_chunk_a;
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BitField<36, 2, VmadType> type_a;
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BitField<36, 2, u64> byte_height_a;
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BitField<49, 1, u64> signed_b;
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BitField<50, 1, u64> use_register_b;
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BitField<30, 1, u64> is_byte_chunk_b;
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BitField<28, 2, VmadType> type_b;
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BitField<28, 2, u64> byte_height_b;
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BitField<51, 2, VmadShr> shr;
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BitField<55, 1, u64> saturate; // Saturates the result (a * b + c)
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BitField<47, 1, u64> cc;
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} vmad;
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union {
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BitField<20, 16, u64> imm20_16;
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BitField<36, 1, u64> product_shift_left;
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@ -1083,6 +1117,7 @@ public:
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IPA,
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OUT_R, // Emit vertex/primitive
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ISBERD,
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VMAD,
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FFMA_IMM, // Fused Multiply and Add
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FFMA_CR,
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FFMA_RC,
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@ -1320,6 +1355,7 @@ private:
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INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
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INST("1111101111100---", Id::OUT_R, Type::Trivial, "OUT_R"),
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INST("1110111111010---", Id::ISBERD, Type::Trivial, "ISBERD"),
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INST("01011111--------", Id::VMAD, Type::Trivial, "VMAD"),
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INST("0011001-1-------", Id::FFMA_IMM, Type::Ffma, "FFMA_IMM"),
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INST("010010011-------", Id::FFMA_CR, Type::Ffma, "FFMA_CR"),
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INST("010100011-------", Id::FFMA_RC, Type::Ffma, "FFMA_RC"),
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@ -2953,6 +2953,88 @@ private:
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LOG_WARNING(HW_GPU, "DEPBAR instruction is stubbed");
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break;
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}
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case OpCode::Id::VMAD: {
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const bool signed_a = instr.vmad.signed_a == 1;
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const bool signed_b = instr.vmad.signed_b == 1;
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const bool result_signed = signed_a || signed_b;
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boost::optional<std::string> forced_result;
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auto Unpack = [&](const std::string& op, bool is_chunk, bool is_signed,
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Tegra::Shader::VmadType type, u64 byte_height) {
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const std::string value = [&]() {
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if (!is_chunk) {
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const auto offset = static_cast<u32>(byte_height * 8);
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return "((" + op + " >> " + std::to_string(offset) + ") & 0xff)";
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}
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const std::string zero = "0";
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switch (type) {
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case Tegra::Shader::VmadType::Size16_Low:
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return '(' + op + " & 0xffff)";
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case Tegra::Shader::VmadType::Size16_High:
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return '(' + op + " >> 16)";
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case Tegra::Shader::VmadType::Size32:
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// TODO(Rodrigo): From my hardware tests it becomes a bit "mad" when
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// this type is used (1 * 1 + 0 == 0x5b800000). Until a better
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// explanation is found: assert.
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UNREACHABLE_MSG("Unimplemented");
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return zero;
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case Tegra::Shader::VmadType::Invalid:
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// Note(Rodrigo): This flag is invalid according to nvdisasm. From my
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// testing (even though it's invalid) this makes the whole instruction
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// assign zero to target register.
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forced_result = boost::make_optional(zero);
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return zero;
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default:
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UNREACHABLE();
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return zero;
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}
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}();
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if (is_signed) {
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return "int(" + value + ')';
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}
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return value;
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};
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const std::string op_a = Unpack(regs.GetRegisterAsInteger(instr.gpr8, 0, false),
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instr.vmad.is_byte_chunk_a != 0, signed_a,
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instr.vmad.type_a, instr.vmad.byte_height_a);
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std::string op_b;
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if (instr.vmad.use_register_b) {
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op_b = Unpack(regs.GetRegisterAsInteger(instr.gpr20, 0, false),
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instr.vmad.is_byte_chunk_b != 0, signed_b, instr.vmad.type_b,
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instr.vmad.byte_height_b);
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} else {
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op_b = '(' +
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std::to_string(signed_b ? static_cast<s16>(instr.alu.GetImm20_16())
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: instr.alu.GetImm20_16()) +
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')';
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}
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const std::string op_c = regs.GetRegisterAsInteger(instr.gpr39, 0, result_signed);
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std::string result;
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if (forced_result) {
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result = *forced_result;
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} else {
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result = '(' + op_a + " * " + op_b + " + " + op_c + ')';
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switch (instr.vmad.shr) {
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case Tegra::Shader::VmadShr::Shr7:
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result = '(' + result + " >> 7)";
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break;
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case Tegra::Shader::VmadShr::Shr15:
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result = '(' + result + " >> 15)";
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break;
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}
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}
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regs.SetRegisterToInteger(instr.gpr0, result_signed, 1, result, 1, 1,
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instr.vmad.saturate == 1, 0, Register::Size::Word,
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instr.vmad.cc);
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break;
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}
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default: {
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LOG_CRITICAL(HW_GPU, "Unhandled instruction: {}", opcode->GetName());
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UNREACHABLE();
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