Merge pull request #3070 from ReinUsesLisp/shader-warnings
shader_ir: Reduce severity of warnings
This commit is contained in:
commit
344d15f61e
7 changed files with 19 additions and 51 deletions
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@ -43,11 +43,11 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
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case OpCode::Id::FMUL_IMM: {
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// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
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if (instr.fmul.tab5cb8_2 != 0) {
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LOG_WARNING(HW_GPU, "FMUL tab5cb8_2({}) is not implemented",
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LOG_DEBUG(HW_GPU, "FMUL tab5cb8_2({}) is not implemented",
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instr.fmul.tab5cb8_2.Value());
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}
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if (instr.fmul.tab5c68_0 != 1) {
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LOG_WARNING(HW_GPU, "FMUL tab5cb8_0({}) is not implemented",
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LOG_DEBUG(HW_GPU, "FMUL tab5cb8_0({}) is not implemented",
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instr.fmul.tab5c68_0.Value());
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}
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@ -144,10 +144,11 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
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case OpCode::Id::RRO_C:
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case OpCode::Id::RRO_R:
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case OpCode::Id::RRO_IMM: {
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LOG_DEBUG(HW_GPU, "(STUBBED) RRO used");
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// Currently RRO is only implemented as a register move.
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op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b);
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SetRegister(bb, instr.gpr0, op_b);
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LOG_WARNING(HW_GPU, "RRO instruction is incomplete");
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break;
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}
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default:
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@ -21,8 +21,8 @@ u32 ShaderIR::DecodeArithmeticHalf(NodeBlock& bb, u32 pc) {
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if (opcode->get().GetId() == OpCode::Id::HADD2_C ||
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opcode->get().GetId() == OpCode::Id::HADD2_R) {
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if (instr.alu_half.ftz != 0) {
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LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
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if (instr.alu_half.ftz == 0) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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}
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@ -19,12 +19,12 @@ u32 ShaderIR::DecodeArithmeticHalfImmediate(NodeBlock& bb, u32 pc) {
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const auto opcode = OpCode::Decode(instr);
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if (opcode->get().GetId() == OpCode::Id::HADD2_IMM) {
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if (instr.alu_half_imm.ftz != 0) {
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LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
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if (instr.alu_half_imm.ftz == 0) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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} else {
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if (instr.alu_half_imm.precision != Tegra::Shader::HalfPrecision::None) {
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LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
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if (instr.alu_half_imm.precision != Tegra::Shader::HalfPrecision::FTZ) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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}
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@ -19,10 +19,10 @@ u32 ShaderIR::DecodeFfma(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(instr.ffma.cc != 0, "FFMA cc not implemented");
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if (instr.ffma.tab5980_0 != 1) {
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LOG_WARNING(HW_GPU, "FFMA tab5980_0({}) not implemented", instr.ffma.tab5980_0.Value());
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LOG_DEBUG(HW_GPU, "FFMA tab5980_0({}) not implemented", instr.ffma.tab5980_0.Value());
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}
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if (instr.ffma.tab5980_1 != 0) {
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LOG_WARNING(HW_GPU, "FFMA tab5980_1({}) not implemented", instr.ffma.tab5980_1.Value());
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LOG_DEBUG(HW_GPU, "FFMA tab5980_1({}) not implemented", instr.ffma.tab5980_1.Value());
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}
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const Node op_a = GetRegister(instr.gpr8);
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@ -20,8 +20,8 @@ u32 ShaderIR::DecodeHalfSet(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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if (instr.hset2.ftz != 0) {
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LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
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if (instr.hset2.ftz == 0) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hset2.type_a);
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@ -19,7 +19,9 @@ u32 ShaderIR::DecodeHalfSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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LOG_DEBUG(HW_GPU, "ftz={}", static_cast<u32>(instr.hsetp2.ftz));
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if (instr.hsetp2.ftz != 0) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a);
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op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a);
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@ -44,10 +44,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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bool is_bindless = false;
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switch (opcode->get().GetId()) {
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case OpCode::Id::TEX: {
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if (instr.tex.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TEX.NODEP implementation is incomplete");
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}
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const TextureType texture_type{instr.tex.texture_type};
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const bool is_array = instr.tex.array != 0;
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const bool is_aoffi = instr.tex.UsesMiscMode(TextureMiscMode::AOFFI);
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@ -62,10 +58,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(instr.tex.UsesMiscMode(TextureMiscMode::AOFFI),
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"AOFFI is not implemented");
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if (instr.tex.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TEX.NODEP implementation is incomplete");
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}
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const TextureType texture_type{instr.tex_b.texture_type};
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const bool is_array = instr.tex_b.array != 0;
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const bool is_aoffi = instr.tex.UsesMiscMode(TextureMiscMode::AOFFI);
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@ -82,10 +74,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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const bool depth_compare = instr.texs.UsesMiscMode(TextureMiscMode::DC);
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const auto process_mode = instr.texs.GetTextureProcessMode();
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if (instr.texs.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TEXS.NODEP implementation is incomplete");
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}
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const Node4 components =
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GetTexsCode(instr, texture_type, process_mode, depth_compare, is_array);
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@ -107,10 +95,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::PTP),
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"PTP is not implemented");
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if (instr.tld4.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TLD4.NODEP implementation is incomplete");
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}
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const auto texture_type = instr.tld4.texture_type.Value();
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const bool depth_compare = is_bindless ? instr.tld4_b.UsesMiscMode(TextureMiscMode::DC)
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: instr.tld4.UsesMiscMode(TextureMiscMode::DC);
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@ -125,9 +109,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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case OpCode::Id::TLD4S: {
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UNIMPLEMENTED_IF_MSG(instr.tld4s.UsesMiscMode(TextureMiscMode::AOFFI),
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"AOFFI is not implemented");
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if (instr.tld4s.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TLD4S.NODEP implementation is incomplete");
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}
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const bool depth_compare = instr.tld4s.UsesMiscMode(TextureMiscMode::DC);
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const Node op_a = GetRegister(instr.gpr8);
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@ -164,10 +145,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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is_bindless = true;
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[[fallthrough]];
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case OpCode::Id::TXQ: {
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if (instr.txq.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TXQ.NODEP implementation is incomplete");
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}
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// TODO: The new commits on the texture refactor, change the way samplers work.
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// Sadly, not all texture instructions specify the type of texture their sampler
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// uses. This must be fixed at a later instance.
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@ -205,10 +182,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(instr.tmml.UsesMiscMode(Tegra::Shader::TextureMiscMode::NDV),
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"NDV is not implemented");
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if (instr.tmml.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TMML.NODEP implementation is incomplete");
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}
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auto texture_type = instr.tmml.texture_type.Value();
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const bool is_array = instr.tmml.array != 0;
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const auto& sampler =
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@ -254,10 +227,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(instr.tld.ms, "MS is not implemented");
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UNIMPLEMENTED_IF_MSG(instr.tld.cl, "CL is not implemented");
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if (instr.tld.nodep_flag) {
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LOG_WARNING(HW_GPU, "TLD.NODEP implementation is incomplete");
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}
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WriteTexInstructionFloat(bb, instr, GetTldCode(instr));
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break;
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}
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@ -269,10 +238,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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"AOFFI is not implemented");
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UNIMPLEMENTED_IF_MSG(instr.tlds.UsesMiscMode(TextureMiscMode::MZ), "MZ is not implemented");
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if (instr.tlds.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TLDS.NODEP implementation is incomplete");
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}
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const Node4 components = GetTldsCode(instr, texture_type, is_array);
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if (instr.tlds.fp32_flag) {
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