98e3274935
PDC0 and PDC1 are both VBlank interrupts. PDC0 was being treated as a HBlank interrupt and fired many more times than it should. They now both fire together at 60 Hz. This puzzlingly *improves* apparent framerate on many applications. A few other interrupts were being fired inside the GSP command processing instead of on the actual GPU register writes, so they were moved there, which should cover direct writes tho those registers not going through the GX command queue. |
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| .. | ||
| assets | ||
| citra | ||
| citra_qt | ||
| common | ||
| core | ||
| video_core | ||
| CMakeLists.txt | ||