5bef54618a
The FPS counter was based on metrics in the nvdisp swapbuffers call. This metric would be accurate if the gpu thread/renderer were synchronous with the nvdisp service, but that's no longer the case. This commit moves the frame counting responsibility onto the concrete renderers after their frame draw calls. Resulting in more meaningful metrics. The displayed FPS is now made up of the average framerate between the previous and most recent update, in order to avoid distracting FPS counter updates when framerate is oscillating between close values. The status bar update frequency was also changed from 2 seconds to 500ms.
442 lines
13 KiB
C++
442 lines
13 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <atomic>
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#include <condition_variable>
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#include <list>
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#include <memory>
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#include <mutex>
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#include "common/common_types.h"
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#include "core/hle/service/nvdrv/nvdata.h"
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#include "core/hle/service/nvflinger/buffer_queue.h"
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#include "video_core/cdma_pusher.h"
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#include "video_core/dma_pusher.h"
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#include "video_core/framebuffer_config.h"
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#include "video_core/gpu_thread.h"
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using CacheAddr = std::uintptr_t;
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[[nodiscard]] inline CacheAddr ToCacheAddr(const void* host_ptr) {
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return reinterpret_cast<CacheAddr>(host_ptr);
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}
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[[nodiscard]] inline u8* FromCacheAddr(CacheAddr cache_addr) {
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return reinterpret_cast<u8*>(cache_addr);
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}
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namespace Core {
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namespace Frontend {
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class EmuWindow;
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}
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class System;
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} // namespace Core
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namespace VideoCore {
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class RendererBase;
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class ShaderNotify;
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} // namespace VideoCore
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namespace Tegra {
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enum class RenderTargetFormat : u32 {
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NONE = 0x0,
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R32B32G32A32_FLOAT = 0xC0,
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R32G32B32A32_SINT = 0xC1,
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R32G32B32A32_UINT = 0xC2,
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R16G16B16A16_UNORM = 0xC6,
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R16G16B16A16_SNORM = 0xC7,
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R16G16B16A16_SINT = 0xC8,
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R16G16B16A16_UINT = 0xC9,
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R16G16B16A16_FLOAT = 0xCA,
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R32G32_FLOAT = 0xCB,
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R32G32_SINT = 0xCC,
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R32G32_UINT = 0xCD,
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R16G16B16X16_FLOAT = 0xCE,
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B8G8R8A8_UNORM = 0xCF,
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B8G8R8A8_SRGB = 0xD0,
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A2B10G10R10_UNORM = 0xD1,
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A2B10G10R10_UINT = 0xD2,
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A8B8G8R8_UNORM = 0xD5,
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A8B8G8R8_SRGB = 0xD6,
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A8B8G8R8_SNORM = 0xD7,
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A8B8G8R8_SINT = 0xD8,
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A8B8G8R8_UINT = 0xD9,
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R16G16_UNORM = 0xDA,
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R16G16_SNORM = 0xDB,
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R16G16_SINT = 0xDC,
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R16G16_UINT = 0xDD,
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R16G16_FLOAT = 0xDE,
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B10G11R11_FLOAT = 0xE0,
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R32_SINT = 0xE3,
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R32_UINT = 0xE4,
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R32_FLOAT = 0xE5,
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R5G6B5_UNORM = 0xE8,
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A1R5G5B5_UNORM = 0xE9,
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R8G8_UNORM = 0xEA,
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R8G8_SNORM = 0xEB,
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R8G8_SINT = 0xEC,
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R8G8_UINT = 0xED,
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R16_UNORM = 0xEE,
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R16_SNORM = 0xEF,
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R16_SINT = 0xF0,
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R16_UINT = 0xF1,
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R16_FLOAT = 0xF2,
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R8_UNORM = 0xF3,
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R8_SNORM = 0xF4,
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R8_SINT = 0xF5,
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R8_UINT = 0xF6,
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};
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enum class DepthFormat : u32 {
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D32_FLOAT = 0xA,
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D16_UNORM = 0x13,
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S8_UINT_Z24_UNORM = 0x14,
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D24X8_UNORM = 0x15,
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D24S8_UNORM = 0x16,
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D24C8_UNORM = 0x18,
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D32_FLOAT_S8X24_UINT = 0x19,
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};
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struct CommandListHeader;
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class DebugContext;
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namespace Engines {
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class Fermi2D;
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class Maxwell3D;
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class MaxwellDMA;
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class KeplerCompute;
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class KeplerMemory;
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} // namespace Engines
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enum class EngineID {
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FERMI_TWOD_A = 0x902D, // 2D Engine
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MAXWELL_B = 0xB197, // 3D Engine
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KEPLER_COMPUTE_B = 0xB1C0,
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KEPLER_INLINE_TO_MEMORY_B = 0xA140,
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MAXWELL_DMA_COPY_A = 0xB0B5,
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};
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class MemoryManager;
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class GPU final {
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public:
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struct MethodCall {
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u32 method{};
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u32 argument{};
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u32 subchannel{};
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u32 method_count{};
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explicit MethodCall(u32 method_, u32 argument_, u32 subchannel_ = 0, u32 method_count_ = 0)
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: method(method_), argument(argument_), subchannel(subchannel_),
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method_count(method_count_) {}
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[[nodiscard]] bool IsLastCall() const {
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return method_count <= 1;
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}
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};
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explicit GPU(Core::System& system_, bool is_async_, bool use_nvdec_);
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~GPU();
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/// Binds a renderer to the GPU.
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void BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer);
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/// Calls a GPU method.
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void CallMethod(const MethodCall& method_call);
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/// Calls a GPU multivalue method.
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void CallMultiMethod(u32 method, u32 subchannel, const u32* base_start, u32 amount,
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u32 methods_pending);
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/// Flush all current written commands into the host GPU for execution.
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void FlushCommands();
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/// Synchronizes CPU writes with Host GPU memory.
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void SyncGuestHost();
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/// Signal the ending of command list.
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void OnCommandListEnd();
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/// Request a host GPU memory flush from the CPU.
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[[nodiscard]] u64 RequestFlush(VAddr addr, std::size_t size);
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/// Obtains current flush request fence id.
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[[nodiscard]] u64 CurrentFlushRequestFence() const {
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return current_flush_fence.load(std::memory_order_relaxed);
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}
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/// Tick pending requests within the GPU.
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void TickWork();
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/// Returns a reference to the Maxwell3D GPU engine.
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[[nodiscard]] Engines::Maxwell3D& Maxwell3D();
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/// Returns a const reference to the Maxwell3D GPU engine.
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[[nodiscard]] const Engines::Maxwell3D& Maxwell3D() const;
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/// Returns a reference to the KeplerCompute GPU engine.
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[[nodiscard]] Engines::KeplerCompute& KeplerCompute();
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/// Returns a reference to the KeplerCompute GPU engine.
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[[nodiscard]] const Engines::KeplerCompute& KeplerCompute() const;
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/// Returns a reference to the GPU memory manager.
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[[nodiscard]] Tegra::MemoryManager& MemoryManager();
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/// Returns a const reference to the GPU memory manager.
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[[nodiscard]] const Tegra::MemoryManager& MemoryManager() const;
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/// Returns a reference to the GPU DMA pusher.
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[[nodiscard]] Tegra::DmaPusher& DmaPusher();
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/// Returns a const reference to the GPU DMA pusher.
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[[nodiscard]] const Tegra::DmaPusher& DmaPusher() const;
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/// Returns a reference to the GPU CDMA pusher.
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[[nodiscard]] Tegra::CDmaPusher& CDmaPusher();
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/// Returns a const reference to the GPU CDMA pusher.
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[[nodiscard]] const Tegra::CDmaPusher& CDmaPusher() const;
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/// Returns a reference to the underlying renderer.
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[[nodiscard]] VideoCore::RendererBase& Renderer() {
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return *renderer;
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}
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/// Returns a const reference to the underlying renderer.
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[[nodiscard]] const VideoCore::RendererBase& Renderer() const {
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return *renderer;
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}
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/// Returns a reference to the shader notifier.
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[[nodiscard]] VideoCore::ShaderNotify& ShaderNotify() {
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return *shader_notify;
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}
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/// Returns a const reference to the shader notifier.
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[[nodiscard]] const VideoCore::ShaderNotify& ShaderNotify() const {
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return *shader_notify;
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}
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// Stops the GPU execution and waits for the GPU to finish working
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void ShutDown();
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/// Allows the CPU/NvFlinger to wait on the GPU before presenting a frame.
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void WaitFence(u32 syncpoint_id, u32 value);
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void IncrementSyncPoint(u32 syncpoint_id);
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[[nodiscard]] u32 GetSyncpointValue(u32 syncpoint_id) const;
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void RegisterSyncptInterrupt(u32 syncpoint_id, u32 value);
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[[nodiscard]] bool CancelSyncptInterrupt(u32 syncpoint_id, u32 value);
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[[nodiscard]] u64 GetTicks() const;
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[[nodiscard]] std::unique_lock<std::mutex> LockSync() {
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return std::unique_lock{sync_mutex};
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}
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[[nodiscard]] bool IsAsync() const {
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return is_async;
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}
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[[nodiscard]] bool UseNvdec() const {
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return use_nvdec;
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}
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void RendererFrameEndNotify();
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enum class FenceOperation : u32 {
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Acquire = 0,
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Increment = 1,
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};
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union FenceAction {
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u32 raw;
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BitField<0, 1, FenceOperation> op;
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BitField<8, 24, u32> syncpoint_id;
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[[nodiscard]] static CommandHeader Build(FenceOperation op, u32 syncpoint_id) {
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FenceAction result{};
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result.op.Assign(op);
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result.syncpoint_id.Assign(syncpoint_id);
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return {result.raw};
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}
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};
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struct Regs {
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static constexpr size_t NUM_REGS = 0x40;
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union {
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struct {
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INSERT_PADDING_WORDS_NOINIT(0x4);
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struct {
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u32 address_high;
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u32 address_low;
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[[nodiscard]] GPUVAddr SemaphoreAddress() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} semaphore_address;
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u32 semaphore_sequence;
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u32 semaphore_trigger;
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INSERT_PADDING_WORDS_NOINIT(0xC);
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// The pusher and the puller share the reference counter, the pusher only has read
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// access
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u32 reference_count;
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INSERT_PADDING_WORDS_NOINIT(0x5);
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u32 semaphore_acquire;
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u32 semaphore_release;
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u32 fence_value;
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FenceAction fence_action;
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INSERT_PADDING_WORDS_NOINIT(0xE2);
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// Puller state
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u32 acquire_mode;
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u32 acquire_source;
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u32 acquire_active;
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u32 acquire_timeout;
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u32 acquire_value;
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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/// Performs any additional setup necessary in order to begin GPU emulation.
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/// This can be used to launch any necessary threads and register any necessary
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/// core timing events.
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void Start();
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/// Obtain the CPU Context
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void ObtainContext();
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/// Release the CPU Context
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void ReleaseContext();
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/// Push GPU command entries to be processed
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void PushGPUEntries(Tegra::CommandList&& entries);
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/// Push GPU command buffer entries to be processed
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void PushCommandBuffer(Tegra::ChCommandHeaderList& entries);
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/// Frees the CDMAPusher instance to free up resources
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void ClearCdmaInstance();
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/// Swap buffers (render frame)
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void SwapBuffers(const Tegra::FramebufferConfig* framebuffer);
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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void FlushRegion(VAddr addr, u64 size);
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/// Notify rasterizer that any caches of the specified region should be invalidated
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void InvalidateRegion(VAddr addr, u64 size);
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/// Notify rasterizer that any caches of the specified region should be flushed and invalidated
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void FlushAndInvalidateRegion(VAddr addr, u64 size);
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protected:
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void TriggerCpuInterrupt(u32 syncpoint_id, u32 value) const;
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private:
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void ProcessBindMethod(const MethodCall& method_call);
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void ProcessFenceActionMethod();
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void ProcessWaitForInterruptMethod();
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void ProcessSemaphoreTriggerMethod();
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void ProcessSemaphoreRelease();
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void ProcessSemaphoreAcquire();
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/// Calls a GPU puller method.
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void CallPullerMethod(const MethodCall& method_call);
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/// Calls a GPU engine method.
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void CallEngineMethod(const MethodCall& method_call);
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/// Calls a GPU engine multivalue method.
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void CallEngineMultiMethod(u32 method, u32 subchannel, const u32* base_start, u32 amount,
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u32 methods_pending);
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/// Determines where the method should be executed.
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[[nodiscard]] bool ExecuteMethodOnEngine(u32 method);
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protected:
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Core::System& system;
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std::unique_ptr<Tegra::MemoryManager> memory_manager;
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std::unique_ptr<Tegra::DmaPusher> dma_pusher;
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std::unique_ptr<Tegra::CDmaPusher> cdma_pusher;
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std::unique_ptr<VideoCore::RendererBase> renderer;
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VideoCore::RasterizerInterface* rasterizer = nullptr;
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const bool use_nvdec;
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private:
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/// Mapping of command subchannels to their bound engine ids
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std::array<EngineID, 8> bound_engines = {};
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/// 3D engine
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std::unique_ptr<Engines::Maxwell3D> maxwell_3d;
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/// 2D engine
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std::unique_ptr<Engines::Fermi2D> fermi_2d;
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/// Compute engine
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std::unique_ptr<Engines::KeplerCompute> kepler_compute;
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/// DMA engine
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std::unique_ptr<Engines::MaxwellDMA> maxwell_dma;
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/// Inline memory engine
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std::unique_ptr<Engines::KeplerMemory> kepler_memory;
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/// Shader build notifier
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std::unique_ptr<VideoCore::ShaderNotify> shader_notify;
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std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> syncpoints{};
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std::array<std::list<u32>, Service::Nvidia::MaxSyncPoints> syncpt_interrupts;
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std::mutex sync_mutex;
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std::mutex device_mutex;
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std::condition_variable sync_cv;
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struct FlushRequest {
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explicit FlushRequest(u64 fence_, VAddr addr_, std::size_t size_)
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: fence{fence_}, addr{addr_}, size{size_} {}
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u64 fence;
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VAddr addr;
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std::size_t size;
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};
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std::list<FlushRequest> flush_requests;
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std::atomic<u64> current_flush_fence{};
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u64 last_flush_fence{};
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std::mutex flush_request_mutex;
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const bool is_async;
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VideoCommon::GPUThread::ThreadManager gpu_thread;
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std::unique_ptr<Core::Frontend::GraphicsContext> cpu_context;
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(GPU::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(semaphore_address, 0x4);
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ASSERT_REG_POSITION(semaphore_sequence, 0x6);
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ASSERT_REG_POSITION(semaphore_trigger, 0x7);
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ASSERT_REG_POSITION(reference_count, 0x14);
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ASSERT_REG_POSITION(semaphore_acquire, 0x1A);
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ASSERT_REG_POSITION(semaphore_release, 0x1B);
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ASSERT_REG_POSITION(fence_value, 0x1C);
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ASSERT_REG_POSITION(fence_action, 0x1D);
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ASSERT_REG_POSITION(acquire_mode, 0x100);
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ASSERT_REG_POSITION(acquire_source, 0x101);
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ASSERT_REG_POSITION(acquire_active, 0x102);
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ASSERT_REG_POSITION(acquire_timeout, 0x103);
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ASSERT_REG_POSITION(acquire_value, 0x104);
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#undef ASSERT_REG_POSITION
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} // namespace Tegra
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