132 lines
3.7 KiB
C++
132 lines
3.7 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV {
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Id EmitSPIRV::EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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if (inst->HasAssociatedPseudoOperation()) {
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throw NotImplementedException("Pseudo-operations on IAdd32");
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}
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return ctx.OpIAdd(ctx.U32[1], a, b);
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}
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void EmitSPIRV::EmitIAdd64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitSPIRV::EmitISub32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpISub(ctx.U32[1], a, b);
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}
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void EmitSPIRV::EmitISub64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitSPIRV::EmitIMul32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpIMul(ctx.U32[1], a, b);
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}
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void EmitSPIRV::EmitINeg32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitIAbs32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitSPIRV::EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
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}
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void EmitSPIRV::EmitShiftRightLogical32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitShiftRightArithmetic32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitBitwiseAnd32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitBitwiseOr32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitBitwiseXor32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitBitFieldInsert(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitBitFieldSExtract(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitSPIRV::EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
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return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
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}
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Id EmitSPIRV::EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSLessThan(ctx.U1, lhs, rhs);
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}
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void EmitSPIRV::EmitULessThan(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitIEqual(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitSLessThanEqual(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitULessThanEqual(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitSPIRV::EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSGreaterThan(ctx.U1, lhs, rhs);
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}
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void EmitSPIRV::EmitUGreaterThan(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitINotEqual(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitSGreaterThanEqual(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitSPIRV::EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpUGreaterThanEqual(ctx.U1, lhs, rhs);
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}
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void EmitSPIRV::EmitLogicalOr(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitLogicalAnd(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitLogicalXor(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitLogicalNot(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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} // namespace Shader::Backend::SPIRV
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