forked from suyu/suyu
GSP: Fix a major regression introduced in ffda035c, due to which no display transfers were triggered at all anymore.
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a3e029fad0
commit
bd798390d5
1 changed files with 13 additions and 4 deletions
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@ -32,7 +32,7 @@ static inline u8* GetCommandBuffer(u32 thread_id) {
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if (0 == g_shared_memory)
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return nullptr;
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return Kernel::GetSharedMemoryPointer(g_shared_memory,
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return Kernel::GetSharedMemoryPointer(g_shared_memory,
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0x800 + (thread_id * sizeof(CommandBuffer)));
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}
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@ -205,8 +205,16 @@ void ExecuteCommand(const Command& command) {
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break;
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}
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// TODO: Check if texture copies are implemented correctly..
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case CommandId::SET_DISPLAY_TRANSFER:
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{
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auto& params = command.image_copy;
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.input_address), params.in_buffer_address >> 3);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.output_address), params.out_buffer_address >> 3);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.input_size), params.in_buffer_size);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.output_size), params.out_buffer_size);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.flags), params.flags);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.trigger), 1);
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// TODO(bunnei): Signalling all of these interrupts here is totally wrong, but it seems to
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// work well enough for running demos. Need to figure out how these all work and trigger
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// them correctly.
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@ -216,7 +224,9 @@ void ExecuteCommand(const Command& command) {
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SignalInterrupt(InterruptId::P3D);
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SignalInterrupt(InterruptId::DMA);
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break;
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}
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// TODO: Check if texture copies are implemented correctly..
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case CommandId::SET_TEXTURE_COPY:
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{
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auto& params = command.image_copy;
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@ -226,8 +236,7 @@ void ExecuteCommand(const Command& command) {
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.output_size), params.out_buffer_size);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.flags), params.flags);
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// TODO: Should this only be ORed with 1 for texture copies?
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// trigger transfer
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// TODO: Should this register be set to 1 or should instead its value be OR-ed with 1?
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.trigger), 1);
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break;
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}
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