forked from suyu/suyu
shader/control_flow: Abstract repeated code chunks in BRX tracking
Remove copied and pasted for cycles into a common templated function.
This commit is contained in:
ReinUsesLisp
parent
ae7dfa93be
commit
46c3047283
1 changed files with 106 additions and 98 deletions
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@ -2,6 +2,7 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <functional>
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#include <list>
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#include <map>
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#include <set>
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@ -16,7 +17,9 @@
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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namespace {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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@ -136,15 +139,13 @@ struct BranchIndirectInfo {
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s32 relative_position{};
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};
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std::optional<BranchIndirectInfo> TrackBranchIndirectInfo(const CFGRebuildState& state,
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u32 start_address, u32 current_position) {
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const u32 shader_start = state.start;
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u32 pos = current_position;
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BranchIndirectInfo result{};
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u64 track_register = 0;
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struct BufferInfo {
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u32 index;
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u32 offset;
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};
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// Step 0 Get BRX Info
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const Instruction instr = {state.program_code[pos]};
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std::optional<std::pair<s32, u64>> GetBRXInfo(const CFGRebuildState& state, u32& pos) {
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const Instruction instr = state.program_code[pos];
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const auto opcode = OpCode::Decode(instr);
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if (opcode->get().GetId() != OpCode::Id::BRX) {
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return std::nullopt;
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@ -152,86 +153,93 @@ std::optional<BranchIndirectInfo> TrackBranchIndirectInfo(const CFGRebuildState&
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if (instr.brx.constant_buffer != 0) {
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return std::nullopt;
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}
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track_register = instr.gpr8.Value();
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result.relative_position = instr.brx.GetBranchExtend();
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pos--;
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bool found_track = false;
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// Step 1 Track LDC
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while (pos >= shader_start) {
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if (IsSchedInstruction(pos, shader_start)) {
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pos--;
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continue;
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}
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const Instruction instr = {state.program_code[pos]};
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const auto opcode = OpCode::Decode(instr);
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if (opcode->get().GetId() == OpCode::Id::LD_C) {
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if (instr.gpr0.Value() == track_register &&
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instr.ld_c.type.Value() == Tegra::Shader::UniformType::Single) {
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result.buffer = instr.cbuf36.index.Value();
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result.offset = static_cast<u32>(instr.cbuf36.GetOffset());
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track_register = instr.gpr8.Value();
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pos--;
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found_track = true;
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break;
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}
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}
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pos--;
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--pos;
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return std::make_pair(instr.brx.GetBranchExtend(), instr.gpr8.Value());
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}
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if (!found_track) {
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return std::nullopt;
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}
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found_track = false;
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// Step 2 Track SHL
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while (pos >= shader_start) {
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if (IsSchedInstruction(pos, shader_start)) {
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pos--;
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template <typename Result>
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std::optional<Result> TrackInstruction(
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const CFGRebuildState& state, u32& pos,
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std::function<bool(Instruction, const OpCode::Matcher&)>&& test,
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std::function<Result(Instruction, const OpCode::Matcher&)>&& pack) {
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for (; pos >= state.start; --pos) {
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if (IsSchedInstruction(pos, state.start)) {
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continue;
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}
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const Instruction instr = state.program_code[pos];
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const auto opcode = OpCode::Decode(instr);
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if (opcode->get().GetId() == OpCode::Id::SHL_IMM) {
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if (instr.gpr0.Value() == track_register) {
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track_register = instr.gpr8.Value();
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pos--;
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found_track = true;
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break;
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}
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}
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pos--;
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}
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if (!found_track) {
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return std::nullopt;
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}
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found_track = false;
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// Step 3 Track IMNMX
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while (pos >= shader_start) {
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if (IsSchedInstruction(pos, shader_start)) {
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pos--;
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if (!opcode) {
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continue;
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}
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const Instruction instr = state.program_code[pos];
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const auto opcode = OpCode::Decode(instr);
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if (opcode->get().GetId() == OpCode::Id::IMNMX_IMM) {
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if (instr.gpr0.Value() == track_register) {
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track_register = instr.gpr8.Value();
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result.entries = instr.alu.GetSignedImm20_20() + 1;
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pos--;
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found_track = true;
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break;
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if (test(instr, opcode->get())) {
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--pos;
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return std::make_optional(pack(instr, opcode->get()));
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}
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}
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pos--;
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}
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if (!found_track) {
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return std::nullopt;
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}
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return result;
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std::optional<std::pair<BufferInfo, u64>> TrackLDC(const CFGRebuildState& state, u32& pos,
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u64 brx_tracked_register) {
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return TrackInstruction<std::pair<BufferInfo, u64>>(
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state, pos,
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[brx_tracked_register](auto instr, auto& opcode) {
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return opcode.GetId() == OpCode::Id::LD_C &&
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instr.gpr0.Value() == brx_tracked_register &&
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instr.ld_c.type.Value() == Tegra::Shader::UniformType::Single;
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},
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[](auto instr, auto& opcode) {
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const BufferInfo info = {static_cast<u32>(instr.cbuf36.index.Value()),
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static_cast<u32>(instr.cbuf36.GetOffset())};
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return std::make_pair(info, instr.gpr8.Value());
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});
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}
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std::optional<u64> TrackSHLRegister(const CFGRebuildState& state, u32& pos,
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u64 ldc_tracked_register) {
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return TrackInstruction<u64>(state, pos,
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[ldc_tracked_register](auto instr, auto& opcode) {
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return opcode.GetId() == OpCode::Id::SHL_IMM &&
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instr.gpr0.Value() == ldc_tracked_register;
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},
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[](auto instr, auto&) { return instr.gpr8.Value(); });
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}
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std::optional<u32> TrackIMNMXValue(const CFGRebuildState& state, u32& pos,
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u64 shl_tracked_register) {
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return TrackInstruction<u32>(
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state, pos,
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[shl_tracked_register](auto instr, auto& opcode) {
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return opcode.GetId() == OpCode::Id::IMNMX_IMM &&
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instr.gpr0.Value() == shl_tracked_register;
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},
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[](auto instr, auto&) { return static_cast<u32>(instr.alu.GetSignedImm20_20() + 1); });
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}
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std::optional<BranchIndirectInfo> TrackBranchIndirectInfo(const CFGRebuildState& state, u32 pos) {
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const auto brx_info = GetBRXInfo(state, pos);
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if (!brx_info) {
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return std::nullopt;
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}
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const auto [relative_position, brx_tracked_register] = *brx_info;
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const auto ldc_info = TrackLDC(state, pos, brx_tracked_register);
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if (!ldc_info) {
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return std::nullopt;
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}
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const auto [buffer_info, ldc_tracked_register] = *ldc_info;
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const auto shl_tracked_register = TrackSHLRegister(state, pos, ldc_tracked_register);
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if (!shl_tracked_register) {
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return std::nullopt;
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}
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const auto entries = TrackIMNMXValue(state, pos, *shl_tracked_register);
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if (!entries) {
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return std::nullopt;
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}
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return BranchIndirectInfo{buffer_info.index, buffer_info.offset, *entries, relative_position};
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}
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std::pair<ParseResult, ParseInfo> ParseCode(CFGRebuildState& state, u32 address) {
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@ -420,17 +428,21 @@ std::pair<ParseResult, ParseInfo> ParseCode(CFGRebuildState& state, u32 address)
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break;
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}
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case OpCode::Id::BRX: {
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auto tmp = TrackBranchIndirectInfo(state, address, offset);
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if (tmp) {
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auto result = *tmp;
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std::vector<CaseBranch> branches{};
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s32 pc_target = offset + result.relative_position;
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for (u32 i = 0; i < result.entries; i++) {
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auto k = state.locker.ObtainKey(result.buffer, result.offset + i * 4);
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if (!k) {
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const auto tmp = TrackBranchIndirectInfo(state, offset);
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if (!tmp) {
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LOG_WARNING(HW_GPU, "BRX Track Unsuccesful");
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return {ParseResult::AbnormalFlow, parse_info};
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}
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u32 value = *k;
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const auto result = *tmp;
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const s32 pc_target = offset + result.relative_position;
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std::vector<CaseBranch> branches;
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for (u32 i = 0; i < result.entries; i++) {
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auto key = state.locker.ObtainKey(result.buffer, result.offset + i * 4);
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if (!key) {
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return {ParseResult::AbnormalFlow, parse_info};
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}
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u32 value = *key;
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u32 target = static_cast<u32>((value >> 3) + pc_target);
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insert_label(state, target);
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branches.emplace_back(value, target);
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@ -440,10 +452,6 @@ std::pair<ParseResult, ParseInfo> ParseCode(CFGRebuildState& state, u32 address)
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static_cast<u32>(instr.gpr8.Value()), std::move(branches));
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return {ParseResult::ControlCaught, parse_info};
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} else {
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LOG_WARNING(HW_GPU, "BRX Track Unsuccesful");
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}
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return {ParseResult::AbnormalFlow, parse_info};
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}
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default:
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break;
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