shader: Fold integer FMA from Nvidia's pattern
Fold shaders doing "a * b + c" on integers from the pattern generated by Nvidia's GL compiler. On a somewhat complex compute shader it reduces the code size by 16 instructions from 2 matches on Turing GPUs. On Intel as extracted from KHR_pipeline_executable_properties: Before the optimization: ``` Instruction Count: 2057 Basic Block Count: 45 Scratch Memory Size: 14752 Spill Count: 232 Fill Count: 261 SEND Count: 610 Cycle Count: 11325 ``` After the optimization: ``` Instruction Count: 2046 Basic Block Count: 44 Scratch Memory Size: 13728 Spill Count: 219 Fill Count: 268 SEND Count: 604 Cycle Count: 11367 ```
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ReinUsesLisp
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1 changed files with 175 additions and 0 deletions
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@ -3,6 +3,7 @@
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// Refer to the license.txt file included.
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <algorithm>
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#include <functional>
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#include <tuple>
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#include <tuple>
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#include <type_traits>
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#include <type_traits>
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@ -88,6 +89,26 @@ bool FoldWhenAllImmediates(IR::Inst& inst, Func&& func) {
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return true;
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return true;
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}
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}
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/// Return true when all values in a range are equal
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template <typename Range>
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bool AreEqual(const Range& range) {
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auto resolver{[](const auto& value) { return value.Resolve(); }};
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auto equal{[](const IR::Value& lhs, const IR::Value& rhs) {
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if (lhs == rhs) {
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return true;
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}
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// Not equal, but try to match if they read the same constant buffer
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if (!lhs.IsImmediate() && !rhs.IsImmediate() &&
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lhs.Inst()->GetOpcode() == IR::Opcode::GetCbufU32 &&
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rhs.Inst()->GetOpcode() == IR::Opcode::GetCbufU32 &&
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lhs.Inst()->Arg(0) == rhs.Inst()->Arg(0) && lhs.Inst()->Arg(1) == rhs.Inst()->Arg(1)) {
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return true;
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}
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return false;
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}};
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return std::ranges::adjacent_find(range, std::not_fn(equal), resolver) == std::end(range);
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}
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void FoldGetRegister(IR::Inst& inst) {
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void FoldGetRegister(IR::Inst& inst) {
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if (inst.Arg(0).Reg() == IR::Reg::RZ) {
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if (inst.Arg(0).Reg() == IR::Reg::RZ) {
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inst.ReplaceUsesWith(IR::Value{u32{0}});
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inst.ReplaceUsesWith(IR::Value{u32{0}});
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@ -100,6 +121,157 @@ void FoldGetPred(IR::Inst& inst) {
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}
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}
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}
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}
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/// Replaces the XMAD pattern generated by an integer FMA
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bool FoldXmadMultiplyAdd(IR::Block& block, IR::Inst& inst) {
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/*
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* We are looking for this specific pattern:
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* %6 = BitFieldUExtract %op_b, #0, #16
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* %7 = BitFieldUExtract %op_a', #16, #16
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* %8 = IMul32 %6, %7
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* %10 = BitFieldUExtract %op_a', #0, #16
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* %11 = BitFieldInsert %8, %10, #16, #16
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* %15 = BitFieldUExtract %op_b, #0, #16
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* %16 = BitFieldUExtract %op_a, #0, #16
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* %17 = IMul32 %15, %16
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* %18 = IAdd32 %17, %op_c
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* %22 = BitFieldUExtract %op_b, #16, #16
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* %23 = BitFieldUExtract %11, #16, #16
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* %24 = IMul32 %22, %23
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* %25 = ShiftLeftLogical32 %24, #16
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* %26 = ShiftLeftLogical32 %11, #16
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* %27 = IAdd32 %26, %18
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* %result = IAdd32 %25, %27
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*
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* And replace it with:
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* %temp = IMul32 %op_a, %op_b
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* %result = IAdd32 %temp, %op_c
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*
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* This optimization has been proven safe by Nvidia's compiler logic being reversed.
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* (If Nvidia generates this code from 'fma(a, b, c)', we can do the same in the reverse order.)
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*/
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const IR::Value zero{0u};
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const IR::Value sixteen{16u};
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IR::Inst* const _25{inst.Arg(0).TryInstRecursive()};
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IR::Inst* const _27{inst.Arg(1).TryInstRecursive()};
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if (!_25 || !_27) {
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return false;
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}
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if (_27->GetOpcode() != IR::Opcode::IAdd32) {
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return false;
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}
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if (_25->GetOpcode() != IR::Opcode::ShiftLeftLogical32 || _25->Arg(1) != sixteen) {
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return false;
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}
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IR::Inst* const _24{_25->Arg(0).TryInstRecursive()};
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if (!_24 || _24->GetOpcode() != IR::Opcode::IMul32) {
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return false;
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}
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IR::Inst* const _22{_24->Arg(0).TryInstRecursive()};
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IR::Inst* const _23{_24->Arg(1).TryInstRecursive()};
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if (!_22 || !_23) {
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return false;
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}
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if (_22->GetOpcode() != IR::Opcode::BitFieldUExtract) {
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return false;
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}
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if (_23->GetOpcode() != IR::Opcode::BitFieldUExtract) {
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return false;
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}
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if (_22->Arg(1) != sixteen || _22->Arg(2) != sixteen) {
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return false;
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}
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if (_23->Arg(1) != sixteen || _23->Arg(2) != sixteen) {
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return false;
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}
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IR::Inst* const _11{_23->Arg(0).TryInstRecursive()};
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if (!_11 || _11->GetOpcode() != IR::Opcode::BitFieldInsert) {
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return false;
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}
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if (_11->Arg(2) != sixteen || _11->Arg(3) != sixteen) {
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return false;
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}
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IR::Inst* const _8{_11->Arg(0).TryInstRecursive()};
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IR::Inst* const _10{_11->Arg(1).TryInstRecursive()};
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if (!_8 || !_10) {
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return false;
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}
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if (_8->GetOpcode() != IR::Opcode::IMul32) {
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return false;
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}
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if (_10->GetOpcode() != IR::Opcode::BitFieldUExtract) {
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return false;
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}
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IR::Inst* const _6{_8->Arg(0).TryInstRecursive()};
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IR::Inst* const _7{_8->Arg(1).TryInstRecursive()};
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if (!_6 || !_7) {
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return false;
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}
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if (_6->GetOpcode() != IR::Opcode::BitFieldUExtract) {
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return false;
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}
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if (_7->GetOpcode() != IR::Opcode::BitFieldUExtract) {
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return false;
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}
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if (_6->Arg(1) != zero || _6->Arg(2) != sixteen) {
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return false;
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}
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if (_7->Arg(1) != sixteen || _7->Arg(2) != sixteen) {
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return false;
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}
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IR::Inst* const _26{_27->Arg(0).TryInstRecursive()};
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IR::Inst* const _18{_27->Arg(1).TryInstRecursive()};
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if (!_26 || !_18) {
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return false;
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}
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if (_26->GetOpcode() != IR::Opcode::ShiftLeftLogical32 || _26->Arg(1) != sixteen) {
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return false;
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}
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if (_26->Arg(0).InstRecursive() != _11) {
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return false;
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}
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if (_18->GetOpcode() != IR::Opcode::IAdd32) {
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return false;
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}
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IR::Inst* const _17{_18->Arg(0).TryInstRecursive()};
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if (!_17 || _17->GetOpcode() != IR::Opcode::IMul32) {
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return false;
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}
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IR::Inst* const _15{_17->Arg(0).TryInstRecursive()};
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IR::Inst* const _16{_17->Arg(1).TryInstRecursive()};
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if (!_15 || !_16) {
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return false;
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}
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if (_15->GetOpcode() != IR::Opcode::BitFieldUExtract) {
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return false;
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}
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if (_16->GetOpcode() != IR::Opcode::BitFieldUExtract) {
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return false;
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}
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if (_15->Arg(1) != zero || _16->Arg(1) != zero || _10->Arg(1) != zero) {
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return false;
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}
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if (_15->Arg(2) != sixteen || _16->Arg(2) != sixteen || _10->Arg(2) != sixteen) {
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return false;
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}
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const std::array<IR::Value, 3> op_as{
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_7->Arg(0).Resolve(),
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_16->Arg(0).Resolve(),
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_10->Arg(0).Resolve(),
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};
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const std::array<IR::Value, 3> op_bs{
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_22->Arg(0).Resolve(),
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_6->Arg(0).Resolve(),
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_15->Arg(0).Resolve(),
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};
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const IR::U32 op_c{_18->Arg(1)};
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if (!AreEqual(op_as) || !AreEqual(op_bs)) {
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return false;
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}
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.ReplaceUsesWith(ir.IAdd(ir.IMul(IR::U32{op_as[0]}, IR::U32{op_bs[1]}), op_c));
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return true;
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}
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/// Replaces the pattern generated by two XMAD multiplications
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/// Replaces the pattern generated by two XMAD multiplications
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bool FoldXmadMultiply(IR::Block& block, IR::Inst& inst) {
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bool FoldXmadMultiply(IR::Block& block, IR::Inst& inst) {
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/*
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/*
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@ -179,6 +351,9 @@ void FoldAdd(IR::Block& block, IR::Inst& inst) {
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if (FoldXmadMultiply(block, inst)) {
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if (FoldXmadMultiply(block, inst)) {
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return;
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return;
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}
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}
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if (FoldXmadMultiplyAdd(block, inst)) {
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return;
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}
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}
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}
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}
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}
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