forked from suyu/suyu
9e87193725
Now that the GPU is initialized when video backends are initialized, it's no longer needed to query components once the game is running: it can be done when yuzu is booting. This allows us to pass components between constructors and in the process remove all Core::System references in the video backend.
76 lines
2.8 KiB
C++
76 lines
2.8 KiB
C++
// Copyright 2020 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <cstddef>
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#include <boost/container_hash/hash.hpp>
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#include "common/common_types.h"
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#include "core/core.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/memory_manager.h"
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#include "video_core/shader/memory_util.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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GPUVAddr GetShaderAddress(Tegra::Engines::Maxwell3D& maxwell3d,
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Tegra::Engines::Maxwell3D::Regs::ShaderProgram program) {
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const auto& shader_config{maxwell3d.regs.shader_config[static_cast<std::size_t>(program)]};
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return maxwell3d.regs.code_address.CodeAddress() + shader_config.offset;
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}
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bool IsSchedInstruction(std::size_t offset, std::size_t main_offset) {
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// Sched instructions appear once every 4 instructions.
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constexpr std::size_t SchedPeriod = 4;
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const std::size_t absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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std::size_t CalculateProgramSize(const ProgramCode& program, bool is_compute) {
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// This is the encoded version of BRA that jumps to itself. All Nvidia
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// shaders end with one.
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static constexpr u64 SELF_JUMPING_BRANCH = 0xE2400FFFFF07000FULL;
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static constexpr u64 MASK = 0xFFFFFFFFFF7FFFFFULL;
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const std::size_t start_offset = is_compute ? KERNEL_MAIN_OFFSET : STAGE_MAIN_OFFSET;
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std::size_t offset = start_offset;
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while (offset < program.size()) {
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const u64 instruction = program[offset];
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if (!IsSchedInstruction(offset, start_offset)) {
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if ((instruction & MASK) == SELF_JUMPING_BRANCH) {
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// End on Maxwell's "nop" instruction
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break;
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}
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if (instruction == 0) {
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break;
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}
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}
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++offset;
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}
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// The last instruction is included in the program size
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return std::min(offset + 1, program.size());
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}
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ProgramCode GetShaderCode(Tegra::MemoryManager& memory_manager, GPUVAddr gpu_addr,
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const u8* host_ptr, bool is_compute) {
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ProgramCode code(VideoCommon::Shader::MAX_PROGRAM_LENGTH);
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ASSERT_OR_EXECUTE(host_ptr != nullptr, { return code; });
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memory_manager.ReadBlockUnsafe(gpu_addr, code.data(), code.size() * sizeof(u64));
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code.resize(CalculateProgramSize(code, is_compute));
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return code;
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}
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u64 GetUniqueIdentifier(Tegra::Engines::ShaderType shader_type, bool is_a, const ProgramCode& code,
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const ProgramCode& code_b) {
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size_t unique_identifier = boost::hash_value(code);
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if (is_a) {
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// VertexA programs include two programs
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boost::hash_combine(unique_identifier, boost::hash_value(code_b));
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}
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return static_cast<u64>(unique_identifier);
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}
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} // namespace VideoCommon::Shader
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