forked from suyu/suyu
38d3a48873
P2R dumps predicate or condition codes state to a register. This is useful for unit testing.
80 lines
2.7 KiB
C++
80 lines
2.7 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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namespace {
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constexpr u64 NUM_PROGRAMMABLE_PREDICATES = 7;
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}
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u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED_IF(instr.p2r_r2p.mode != Tegra::Shader::R2pMode::Pr);
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const Node apply_mask = [&] {
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switch (opcode->get().GetId()) {
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case OpCode::Id::R2P_IMM:
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case OpCode::Id::P2R_IMM:
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return Immediate(static_cast<u32>(instr.p2r_r2p.immediate_mask));
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default:
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UNREACHABLE();
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return Immediate(0);
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}
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}();
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const auto offset = static_cast<u32>(instr.p2r_r2p.byte) * 8;
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switch (opcode->get().GetId()) {
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case OpCode::Id::R2P_IMM: {
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const Node mask = GetRegister(instr.gpr8);
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for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) {
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const auto shift = static_cast<u32>(pred);
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const Node apply_compare = BitfieldExtract(apply_mask, shift, 1);
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const Node condition =
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Operation(OperationCode::LogicalUNotEqual, apply_compare, Immediate(0));
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const Node value_compare = BitfieldExtract(mask, offset + shift, 1);
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const Node value =
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Operation(OperationCode::LogicalUNotEqual, value_compare, Immediate(0));
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const Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), value);
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bb.push_back(Conditional(condition, {code}));
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}
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break;
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}
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case OpCode::Id::P2R_IMM: {
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Node value = Immediate(0);
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for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) {
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Node bit = Operation(OperationCode::Select, GetPredicate(pred), Immediate(1U << pred),
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Immediate(0));
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value = Operation(OperationCode::UBitwiseOr, std::move(value), std::move(bit));
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}
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value = Operation(OperationCode::UBitwiseAnd, std::move(value), apply_mask);
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value = BitfieldInsert(GetRegister(instr.gpr8), std::move(value), offset, 8);
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SetRegister(bb, instr.gpr0, std::move(value));
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled P2R/R2R instruction: {}", opcode->get().GetName());
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break;
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}
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return pc;
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}
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} // namespace VideoCommon::Shader
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