forked from suyu/suyu
135 lines
4.2 KiB
C++
135 lines
4.2 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class SelectMode : u64 {
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Default,
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CLO,
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CHI,
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CSFU,
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CBCC,
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};
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enum class Half : u64 {
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H0, // Least-significant bits (15:0)
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H1, // Most-significant bits (31:16)
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};
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IR::U32 ExtractHalf(TranslatorVisitor& v, const IR::U32& src, Half half, bool is_signed) {
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const IR::U32 offset{v.ir.Imm32(half == Half::H1 ? 16 : 0)};
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return v.ir.BitFieldExtract(src, offset, v.ir.Imm32(16), is_signed);
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}
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void XMAD(TranslatorVisitor& v, u64 insn, const IR::U32& src_b, const IR::U32& src_c,
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SelectMode select_mode, Half half_b, bool psl, bool mrg, bool x) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<47, 1, u64> cc;
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BitField<48, 1, u64> is_a_signed;
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BitField<49, 1, u64> is_b_signed;
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BitField<53, 1, Half> half_a;
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} const xmad{insn};
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if (x) {
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throw NotImplementedException("XMAD X");
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}
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const IR::U32 op_a{ExtractHalf(v, v.X(xmad.src_reg_a), xmad.half_a, xmad.is_a_signed != 0)};
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const IR::U32 op_b{ExtractHalf(v, src_b, half_b, xmad.is_b_signed != 0)};
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IR::U32 product{v.ir.IMul(op_a, op_b)};
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if (psl) {
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// .PSL shifts the product 16 bits
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product = v.ir.ShiftLeftLogical(product, v.ir.Imm32(16));
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}
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const IR::U32 op_c{[&]() -> IR::U32 {
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switch (select_mode) {
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case SelectMode::Default:
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return src_c;
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case SelectMode::CLO:
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return ExtractHalf(v, src_c, Half::H0, false);
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case SelectMode::CHI:
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return ExtractHalf(v, src_c, Half::H1, false);
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case SelectMode::CBCC:
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return v.ir.IAdd(v.ir.ShiftLeftLogical(src_b, v.ir.Imm32(16)), src_c);
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case SelectMode::CSFU:
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throw NotImplementedException("XMAD CSFU");
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}
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throw NotImplementedException("Invalid XMAD select mode {}", select_mode);
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}()};
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IR::U32 result{v.ir.IAdd(product, op_c)};
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if (mrg) {
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// .MRG inserts src_b [15:0] into result's [31:16].
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const IR::U32 lsb_b{ExtractHalf(v, src_b, Half::H0, false)};
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result = v.ir.BitFieldInsert(result, lsb_b, v.ir.Imm32(16), v.ir.Imm32(16));
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}
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if (xmad.cc) {
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throw NotImplementedException("XMAD CC");
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}
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// Store result
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v.X(xmad.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::XMAD_reg(u64 insn) {
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union {
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u64 raw;
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BitField<35, 1, Half> half_b;
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BitField<36, 1, u64> psl;
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BitField<37, 1, u64> mrg;
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BitField<38, 1, u64> x;
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BitField<50, 3, SelectMode> select_mode;
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} const xmad{insn};
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XMAD(*this, insn, GetReg20(insn), GetReg39(insn), xmad.select_mode, xmad.half_b, xmad.psl != 0,
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xmad.mrg != 0, xmad.x != 0);
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}
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void TranslatorVisitor::XMAD_rc(u64 insn) {
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union {
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u64 raw;
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BitField<50, 2, SelectMode> select_mode;
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BitField<52, 1, Half> half_b;
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BitField<54, 1, u64> x;
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} const xmad{insn};
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XMAD(*this, insn, GetReg39(insn), GetCbuf(insn), xmad.select_mode, xmad.half_b, false, false,
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xmad.x != 0);
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}
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void TranslatorVisitor::XMAD_cr(u64 insn) {
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union {
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u64 raw;
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BitField<50, 2, SelectMode> select_mode;
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BitField<52, 1, Half> half_b;
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BitField<54, 1, u64> x;
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BitField<55, 1, u64> psl;
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BitField<56, 1, u64> mrg;
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} const xmad{insn};
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XMAD(*this, insn, GetCbuf(insn), GetReg39(insn), xmad.select_mode, xmad.half_b, xmad.psl != 0,
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xmad.mrg != 0, xmad.x != 0);
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}
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void TranslatorVisitor::XMAD_imm(u64 insn) {
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union {
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u64 raw;
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BitField<20, 16, u64> src_b;
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BitField<36, 1, u64> psl;
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BitField<37, 1, u64> mrg;
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BitField<38, 1, u64> x;
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BitField<50, 3, SelectMode> select_mode;
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} const xmad{insn};
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XMAD(*this, insn, ir.Imm32(static_cast<u32>(xmad.src_b)), GetReg39(insn), xmad.select_mode,
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Half::H0, xmad.psl != 0, xmad.mrg != 0, xmad.x != 0);
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}
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} // namespace Shader::Maxwell
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