forked from suyu/suyu
62 lines
1.9 KiB
C++
62 lines
1.9 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<39, 1, u64> is_wrapped;
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BitField<40, 1, u64> brev;
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BitField<43, 1, u64> xmode;
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BitField<48, 1, u64> is_signed;
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} const shr{insn};
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if (shr.xmode != 0) {
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throw NotImplementedException("SHR.XMODE");
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}
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IR::U32 base{v.X(shr.src_reg_a)};
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if (shr.brev == 1) {
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base = v.ir.BitReverse(base);
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}
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IR::U32 result;
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const IR::U32 safe_shift = shr.is_wrapped == 0 ? shift : v.ir.BitwiseAnd(shift, v.ir.Imm32(31));
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if (shr.is_signed == 1) {
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result = IR::U32{v.ir.ShiftRightArithmetic(base, safe_shift)};
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} else {
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result = IR::U32{v.ir.ShiftRightLogical(base, safe_shift)};
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}
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if (shr.is_wrapped == 0) {
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const IR::U32 zero{v.ir.Imm32(0)};
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const IR::U32 safe_bits{v.ir.Imm32(32)};
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const IR::U1 is_negative{v.ir.ILessThan(result, zero, true)};
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const IR::U1 is_safe{v.ir.ILessThan(shift, safe_bits, false)};
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const IR::U32 clamped_value{v.ir.Select(is_negative, v.ir.Imm32(-1), zero)};
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result = IR::U32{v.ir.Select(is_safe, result, clamped_value)};
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}
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v.X(shr.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::SHR_reg(u64 insn) {
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SHR(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::SHR_cbuf(u64 insn) {
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SHR(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::SHR_imm(u64 insn) {
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SHR(*this, insn, GetImm20(insn));
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}
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} // namespace Shader::Maxwell
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