forked from suyu/suyu
114 lines
2.9 KiB
C++
114 lines
2.9 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class SpecialRegister : u64 {
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SR_LANEID = 0,
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SR_VIRTCFG = 2,
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SR_VIRTID = 3,
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SR_PM0 = 4,
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SR_PM1 = 5,
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SR_PM2 = 6,
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SR_PM3 = 7,
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SR_PM4 = 8,
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SR_PM5 = 9,
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SR_PM6 = 10,
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SR_PM7 = 11,
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SR_ORDERING_TICKET = 15,
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SR_PRIM_TYPE = 16,
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SR_INVOCATION_ID = 17,
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SR_Y_DIRECTION = 18,
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SR_THREAD_KILL = 19,
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SM_SHADER_TYPE = 20,
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SR_DIRECTCBEWRITEADDRESSLOW = 21,
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SR_DIRECTCBEWRITEADDRESSHIGH = 22,
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SR_DIRECTCBEWRITEENABLE = 23,
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SR_MACHINE_ID_0 = 24,
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SR_MACHINE_ID_1 = 25,
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SR_MACHINE_ID_2 = 26,
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SR_MACHINE_ID_3 = 27,
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SR_AFFINITY = 28,
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SR_INVOCATION_INFO = 29,
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SR_WSCALEFACTOR_XY = 30,
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SR_WSCALEFACTOR_Z = 31,
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SR_TID = 32,
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SR_TID_X = 33,
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SR_TID_Y = 34,
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SR_TID_Z = 35,
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SR_CTAID_X = 37,
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SR_CTAID_Y = 38,
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SR_CTAID_Z = 39,
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SR_NTID = 49,
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SR_CirQueueIncrMinusOne = 50,
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SR_NLATC = 51,
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SR_SWINLO = 57,
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SR_SWINSZ = 58,
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SR_SMEMSZ = 59,
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SR_SMEMBANKS = 60,
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SR_LWINLO = 61,
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SR_LWINSZ = 62,
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SR_LMEMLOSZ = 63,
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SR_LMEMHIOFF = 64,
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SR_EQMASK = 65,
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SR_LTMASK = 66,
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SR_LEMASK = 67,
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SR_GTMASK = 68,
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SR_GEMASK = 69,
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SR_REGALLOC = 70,
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SR_GLOBALERRORSTATUS = 73,
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SR_WARPERRORSTATUS = 75,
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SR_PM_HI0 = 81,
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SR_PM_HI1 = 82,
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SR_PM_HI2 = 83,
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SR_PM_HI3 = 84,
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SR_PM_HI4 = 85,
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SR_PM_HI5 = 86,
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SR_PM_HI6 = 87,
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SR_PM_HI7 = 88,
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SR_CLOCKLO = 89,
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SR_CLOCKHI = 90,
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SR_GLOBALTIMERLO = 91,
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SR_GLOBALTIMERHI = 92,
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SR_HWTASKID = 105,
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SR_CIRCULARQUEUEENTRYINDEX = 106,
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SR_CIRCULARQUEUEENTRYADDRESSLOW = 107,
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SR_CIRCULARQUEUEENTRYADDRESSHIGH = 108,
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};
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[[nodiscard]] IR::U32 Read(IR::IREmitter& ir, SpecialRegister special_register) {
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switch (special_register) {
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case SpecialRegister::SR_TID_X:
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return ir.LocalInvocationIdX();
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case SpecialRegister::SR_TID_Y:
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return ir.LocalInvocationIdY();
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case SpecialRegister::SR_TID_Z:
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return ir.LocalInvocationIdZ();
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case SpecialRegister::SR_CTAID_X:
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return ir.WorkgroupIdX();
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case SpecialRegister::SR_CTAID_Y:
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return ir.WorkgroupIdY();
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case SpecialRegister::SR_CTAID_Z:
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return ir.WorkgroupIdZ();
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default:
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throw NotImplementedException("S2R special register {}", special_register);
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}
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}
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} // Anonymous namespace
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void TranslatorVisitor::S2R(u64 insn) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<20, 8, SpecialRegister> src_reg;
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} const s2r{insn};
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X(s2r.dest_reg, Read(ir, s2r.src_reg));
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}
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} // namespace Shader::Maxwell
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