forked from suyu/suyu
127 lines
5.5 KiB
C++
127 lines
5.5 KiB
C++
// Copyright 2018 yuzu emulator team
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <vector>
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#include "common/common_types.h"
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#include "common/swap.h"
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#include "core/hle/service/nvdrv/devices/nvdevice.h"
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namespace Service::Nvidia::Devices {
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class nvhost_ctrl_gpu final : public nvdevice {
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public:
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nvhost_ctrl_gpu() = default;
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~nvhost_ctrl_gpu() override = default;
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u32 ioctl(Ioctl command, const std::vector<u8>& input, std::vector<u8>& output) override;
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private:
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enum class IoctlCommand : u32_le {
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IocGetCharacteristicsCommand = 0xC0B04705,
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IocGetTPCMasksCommand = 0xC0184706,
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IocGetActiveSlotMaskCommand = 0x80084714,
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IocZcullGetCtxSizeCommand = 0x80044701,
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IocZcullGetInfo = 0x80284702,
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};
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struct IoctlGpuCharacteristics {
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u32_le arch; // 0x120 (NVGPU_GPU_ARCH_GM200)
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u32_le impl; // 0xB (NVGPU_GPU_IMPL_GM20B)
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u32_le rev; // 0xA1 (Revision A1)
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u32_le num_gpc; // 0x1
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u64_le l2_cache_size; // 0x40000
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u64_le on_board_video_memory_size; // 0x0 (not used)
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u32_le num_tpc_per_gpc; // 0x2
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u32_le bus_type; // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
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u32_le big_page_size; // 0x20000
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u32_le compression_page_size; // 0x20000
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u32_le pde_coverage_bit_count; // 0x1B
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u32_le available_big_page_sizes; // 0x30000
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u32_le gpc_mask; // 0x1
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u32_le sm_arch_sm_version; // 0x503 (Maxwell Generation 5.0.3?)
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u32_le sm_arch_spa_version; // 0x503 (Maxwell Generation 5.0.3?)
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u32_le sm_arch_warp_count; // 0x80
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u32_le gpu_va_bit_count; // 0x28
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u32_le reserved; // NULL
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u64_le flags; // 0x55
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u32_le twod_class; // 0x902D (FERMI_TWOD_A)
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u32_le threed_class; // 0xB197 (MAXWELL_B)
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u32_le compute_class; // 0xB1C0 (MAXWELL_COMPUTE_B)
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u32_le gpfifo_class; // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
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u32_le inline_to_memory_class; // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
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u32_le dma_copy_class; // 0xB0B5 (MAXWELL_DMA_COPY_A)
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u32_le max_fbps_count; // 0x1
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u32_le fbp_en_mask; // 0x0 (disabled)
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u32_le max_ltc_per_fbp; // 0x2
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u32_le max_lts_per_ltc; // 0x1
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u32_le max_tex_per_tpc; // 0x0 (not supported)
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u32_le max_gpc_count; // 0x1
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u32_le rop_l2_en_mask_0; // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
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u32_le rop_l2_en_mask_1; // 0x0
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u64_le chipname; // 0x6230326D67 ("gm20b")
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u64_le gr_compbit_store_base_hw; // 0x0 (not supported)
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};
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static_assert(sizeof(IoctlGpuCharacteristics) == 160,
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"IoctlGpuCharacteristics is incorrect size");
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struct IoctlCharacteristics {
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u64_le gpu_characteristics_buf_size; // must not be NULL, but gets overwritten with
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// 0xA0=max_size
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u64_le gpu_characteristics_buf_addr; // ignored, but must not be NULL
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IoctlGpuCharacteristics gc;
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};
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static_assert(sizeof(IoctlCharacteristics) == 16 + sizeof(IoctlGpuCharacteristics),
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"IoctlCharacteristics is incorrect size");
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struct IoctlGpuGetTpcMasksArgs {
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/// [in] TPC mask buffer size reserved by userspace. Should be at least
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/// sizeof(__u32) * fls(gpc_mask) to receive TPC mask for each GPC.
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/// [out] full kernel buffer size
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u32_le mask_buf_size;
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u32_le reserved;
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/// [in] pointer to TPC mask buffer. It will receive one 32-bit TPC mask per GPC or 0 if
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/// GPC is not enabled or not present. This parameter is ignored if mask_buf_size is 0.
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u64_le mask_buf_addr;
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u64_le tpc_mask_size; // Nintendo add this?
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};
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static_assert(sizeof(IoctlGpuGetTpcMasksArgs) == 24,
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"IoctlGpuGetTpcMasksArgs is incorrect size");
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struct IoctlActiveSlotMask {
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u32_le slot; // always 0x07
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u32_le mask;
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};
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static_assert(sizeof(IoctlActiveSlotMask) == 8, "IoctlActiveSlotMask is incorrect size");
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struct IoctlZcullGetCtxSize {
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u32_le size;
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};
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static_assert(sizeof(IoctlZcullGetCtxSize) == 4, "IoctlZcullGetCtxSize is incorrect size");
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struct IoctlNvgpuGpuZcullGetInfoArgs {
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u32_le width_align_pixels;
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u32_le height_align_pixels;
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u32_le pixel_squares_by_aliquots;
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u32_le aliquot_total;
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u32_le region_byte_multiplier;
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u32_le region_header_size;
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u32_le subregion_header_size;
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u32_le subregion_width_align_pixels;
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u32_le subregion_height_align_pixels;
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u32_le subregion_count;
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};
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static_assert(sizeof(IoctlNvgpuGpuZcullGetInfoArgs) == 40,
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"IoctlNvgpuGpuZcullGetInfoArgs is incorrect size");
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u32 GetCharacteristics(const std::vector<u8>& input, std::vector<u8>& output);
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u32 GetTPCMasks(const std::vector<u8>& input, std::vector<u8>& output);
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u32 GetActiveSlotMask(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ZCullGetCtxSize(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ZCullGetInfo(const std::vector<u8>& input, std::vector<u8>& output);
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};
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} // namespace Service::Nvidia::Devices
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