forked from suyu/suyu
ffc5ec6fa8
P2R CC takes the state of condition codes and puts them into a register. We already have this implemented for PR (predicates). This commit implements CC over that.
86 lines
2.9 KiB
C++
86 lines
2.9 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <utility>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using std::move;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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namespace {
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constexpr u64 NUM_CONDITION_CODES = 4;
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constexpr u64 NUM_PREDICATES = 7;
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} // namespace
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u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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Node apply_mask = [this, opcode, instr] {
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switch (opcode->get().GetId()) {
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case OpCode::Id::R2P_IMM:
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case OpCode::Id::P2R_IMM:
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return Immediate(static_cast<u32>(instr.p2r_r2p.immediate_mask));
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default:
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UNREACHABLE();
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return Immediate(0);
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}
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}();
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const u32 offset = static_cast<u32>(instr.p2r_r2p.byte) * 8;
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const bool cc = instr.p2r_r2p.mode == Tegra::Shader::R2pMode::Cc;
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const u64 num_entries = cc ? NUM_CONDITION_CODES : NUM_PREDICATES;
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const auto get_entry = [this, cc](u64 entry) {
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return cc ? GetInternalFlag(static_cast<InternalFlag>(entry)) : GetPredicate(entry);
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};
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switch (opcode->get().GetId()) {
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case OpCode::Id::R2P_IMM: {
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Node mask = GetRegister(instr.gpr8);
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for (u64 entry = 0; entry < num_entries; ++entry) {
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const u32 shift = static_cast<u32>(entry);
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Node apply = BitfieldExtract(apply_mask, shift, 1);
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Node condition = Operation(OperationCode::LogicalUNotEqual, apply, Immediate(0));
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Node compare = BitfieldExtract(mask, offset + shift, 1);
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Node value = Operation(OperationCode::LogicalUNotEqual, move(compare), Immediate(0));
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Node code = Operation(OperationCode::LogicalAssign, get_entry(entry), move(value));
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bb.push_back(Conditional(condition, {move(code)}));
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}
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break;
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}
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case OpCode::Id::P2R_IMM: {
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Node value = Immediate(0);
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for (u64 entry = 0; entry < num_entries; ++entry) {
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Node bit = Operation(OperationCode::Select, get_entry(entry), Immediate(1U << entry),
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Immediate(0));
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value = Operation(OperationCode::UBitwiseOr, move(value), move(bit));
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}
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value = Operation(OperationCode::UBitwiseAnd, move(value), apply_mask);
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value = BitfieldInsert(GetRegister(instr.gpr8), move(value), offset, 8);
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SetRegister(bb, instr.gpr0, move(value));
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled P2R/R2R instruction: {}", opcode->get().GetName());
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break;
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}
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return pc;
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}
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} // namespace VideoCommon::Shader
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