forked from suyu/suyu
974 lines
38 KiB
C++
974 lines
38 KiB
C++
// Copyright 2019 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <array>
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#include <memory>
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#include <mutex>
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#include <vector>
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#include "common/alignment.h"
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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#include "common/scope_exit.h"
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#include "common/settings.h"
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#include "core/core.h"
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#include "video_core/engines/kepler_compute.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/renderer_vulkan/blit_image.h"
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#include "video_core/renderer_vulkan/fixed_pipeline_state.h"
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#include "video_core/renderer_vulkan/maxwell_to_vk.h"
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#include "video_core/renderer_vulkan/renderer_vulkan.h"
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#include "video_core/renderer_vulkan/vk_buffer_cache.h"
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#include "video_core/renderer_vulkan/vk_compute_pipeline.h"
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#include "video_core/renderer_vulkan/vk_descriptor_pool.h"
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#include "video_core/renderer_vulkan/vk_pipeline_cache.h"
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#include "video_core/renderer_vulkan/vk_rasterizer.h"
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#include "video_core/renderer_vulkan/vk_scheduler.h"
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#include "video_core/renderer_vulkan/vk_staging_buffer_pool.h"
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#include "video_core/renderer_vulkan/vk_state_tracker.h"
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#include "video_core/renderer_vulkan/vk_texture_cache.h"
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#include "video_core/renderer_vulkan/vk_update_descriptor.h"
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#include "video_core/shader_cache.h"
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#include "video_core/texture_cache/texture_cache_base.h"
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#include "video_core/vulkan_common/vulkan_device.h"
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#include "video_core/vulkan_common/vulkan_wrapper.h"
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namespace Vulkan {
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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using VideoCommon::ImageViewId;
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using VideoCommon::ImageViewType;
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MICROPROFILE_DEFINE(Vulkan_WaitForWorker, "Vulkan", "Wait for worker", MP_RGB(255, 192, 192));
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MICROPROFILE_DEFINE(Vulkan_Drawing, "Vulkan", "Record drawing", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_Compute, "Vulkan", "Record compute", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_Clearing, "Vulkan", "Record clearing", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_PipelineCache, "Vulkan", "Pipeline cache", MP_RGB(192, 128, 128));
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namespace {
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struct DrawParams {
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u32 base_instance;
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u32 num_instances;
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u32 base_vertex;
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u32 num_vertices;
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u32 first_index;
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bool is_indexed;
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};
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VkViewport GetViewportState(const Device& device, const Maxwell& regs, size_t index, float scale) {
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const auto& src = regs.viewport_transform[index];
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const auto conv = [scale](float value) {
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float new_value = value * scale;
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if (scale < 1.0f) {
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const bool sign = std::signbit(value);
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new_value = std::round(std::abs(new_value));
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new_value = sign ? -new_value : new_value;
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}
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return new_value;
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};
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const float x = conv(src.translate_x - src.scale_x);
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const float width = conv(src.scale_x * 2.0f);
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float y = conv(src.translate_y - src.scale_y);
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float height = conv(src.scale_y * 2.0f);
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if (regs.screen_y_control.y_negate) {
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y += height;
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height = -height;
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}
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const float reduce_z = regs.depth_mode == Maxwell::DepthMode::MinusOneToOne ? 1.0f : 0.0f;
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VkViewport viewport{
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.x = x,
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.y = y,
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.width = width != 0.0f ? width : 1.0f,
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.height = height != 0.0f ? height : 1.0f,
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.minDepth = src.translate_z - src.scale_z * reduce_z,
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.maxDepth = src.translate_z + src.scale_z,
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};
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if (!device.IsExtDepthRangeUnrestrictedSupported()) {
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viewport.minDepth = std::clamp(viewport.minDepth, 0.0f, 1.0f);
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viewport.maxDepth = std::clamp(viewport.maxDepth, 0.0f, 1.0f);
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}
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return viewport;
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}
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VkRect2D GetScissorState(const Maxwell& regs, size_t index, u32 up_scale = 1, u32 down_shift = 0) {
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const auto& src = regs.scissor_test[index];
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VkRect2D scissor;
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const auto scale_up = [&](s32 value) -> s32 {
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if (value == 0) {
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return 0U;
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}
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const s32 upset = value * up_scale;
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s32 acumm = 0;
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if ((up_scale >> down_shift) == 0) {
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acumm = upset % 2;
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}
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const s32 converted_value = (value * up_scale) >> down_shift;
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return value < 0 ? std::min<s32>(converted_value - acumm, -1)
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: std::max<s32>(converted_value + acumm, 1);
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};
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if (src.enable) {
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scissor.offset.x = scale_up(static_cast<s32>(src.min_x));
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scissor.offset.y = scale_up(static_cast<s32>(src.min_y));
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scissor.extent.width = scale_up(src.max_x - src.min_x);
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scissor.extent.height = scale_up(src.max_y - src.min_y);
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} else {
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scissor.offset.x = 0;
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scissor.offset.y = 0;
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scissor.extent.width = std::numeric_limits<s32>::max();
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scissor.extent.height = std::numeric_limits<s32>::max();
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}
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return scissor;
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}
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DrawParams MakeDrawParams(const Maxwell& regs, u32 num_instances, bool is_instanced,
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bool is_indexed) {
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DrawParams params{
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.base_instance = regs.vb_base_instance,
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.num_instances = is_instanced ? num_instances : 1,
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.base_vertex = is_indexed ? regs.vb_element_base : regs.vertex_buffer.first,
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.num_vertices = is_indexed ? regs.index_array.count : regs.vertex_buffer.count,
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.first_index = is_indexed ? regs.index_array.first : 0,
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.is_indexed = is_indexed,
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};
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if (regs.draw.topology == Maxwell::PrimitiveTopology::Quads) {
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// 6 triangle vertices per quad, base vertex is part of the index
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// See BindQuadArrayIndexBuffer for more details
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params.num_vertices = (params.num_vertices / 4) * 6;
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params.base_vertex = 0;
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params.is_indexed = true;
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}
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return params;
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}
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} // Anonymous namespace
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RasterizerVulkan::RasterizerVulkan(Core::Frontend::EmuWindow& emu_window_, Tegra::GPU& gpu_,
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Tegra::MemoryManager& gpu_memory_,
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Core::Memory::Memory& cpu_memory_, VKScreenInfo& screen_info_,
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const Device& device_, MemoryAllocator& memory_allocator_,
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StateTracker& state_tracker_, VKScheduler& scheduler_)
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: RasterizerAccelerated{cpu_memory_}, gpu{gpu_},
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gpu_memory{gpu_memory_}, maxwell3d{gpu.Maxwell3D()}, kepler_compute{gpu.KeplerCompute()},
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screen_info{screen_info_}, device{device_}, memory_allocator{memory_allocator_},
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state_tracker{state_tracker_}, scheduler{scheduler_},
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staging_pool(device, memory_allocator, scheduler), descriptor_pool(device, scheduler),
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update_descriptor_queue(device, scheduler),
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blit_image(device, scheduler, state_tracker, descriptor_pool),
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astc_decoder_pass(device, scheduler, descriptor_pool, staging_pool, update_descriptor_queue,
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memory_allocator),
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render_pass_cache(device), texture_cache_runtime{device, scheduler,
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memory_allocator, staging_pool,
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blit_image, astc_decoder_pass,
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render_pass_cache},
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texture_cache(texture_cache_runtime, *this, maxwell3d, kepler_compute, gpu_memory),
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buffer_cache_runtime(device, memory_allocator, scheduler, staging_pool,
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update_descriptor_queue, descriptor_pool),
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buffer_cache(*this, maxwell3d, kepler_compute, gpu_memory, cpu_memory_, buffer_cache_runtime),
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pipeline_cache(*this, maxwell3d, kepler_compute, gpu_memory, device, scheduler,
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descriptor_pool, update_descriptor_queue, render_pass_cache, buffer_cache,
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texture_cache, gpu.ShaderNotify()),
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query_cache{*this, maxwell3d, gpu_memory, device, scheduler}, accelerate_dma{buffer_cache},
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fence_manager(*this, gpu, texture_cache, buffer_cache, query_cache, device, scheduler),
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wfi_event(device.GetLogical().CreateEvent()) {
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scheduler.SetQueryCache(query_cache);
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}
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RasterizerVulkan::~RasterizerVulkan() = default;
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void RasterizerVulkan::Draw(bool is_indexed, bool is_instanced) {
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MICROPROFILE_SCOPE(Vulkan_Drawing);
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SCOPE_EXIT({ gpu.TickWork(); });
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FlushWork();
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query_cache.UpdateCounters();
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GraphicsPipeline* const pipeline{pipeline_cache.CurrentGraphicsPipeline()};
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if (!pipeline) {
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return;
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}
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std::scoped_lock lock{buffer_cache.mutex, texture_cache.mutex};
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pipeline->Configure(is_indexed);
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BeginTransformFeedback();
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UpdateDynamicStates();
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const auto& regs{maxwell3d.regs};
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const u32 num_instances{maxwell3d.mme_draw.instance_count};
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const DrawParams draw_params{MakeDrawParams(regs, num_instances, is_instanced, is_indexed)};
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scheduler.Record([draw_params](vk::CommandBuffer cmdbuf) {
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if (draw_params.is_indexed) {
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cmdbuf.DrawIndexed(draw_params.num_vertices, draw_params.num_instances,
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draw_params.first_index, draw_params.base_vertex,
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draw_params.base_instance);
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} else {
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cmdbuf.Draw(draw_params.num_vertices, draw_params.num_instances,
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draw_params.base_vertex, draw_params.base_instance);
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}
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});
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EndTransformFeedback();
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}
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void RasterizerVulkan::Clear() {
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MICROPROFILE_SCOPE(Vulkan_Clearing);
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if (!maxwell3d.ShouldExecute()) {
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return;
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}
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FlushWork();
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query_cache.UpdateCounters();
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auto& regs = maxwell3d.regs;
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const bool use_color = regs.clear_buffers.R || regs.clear_buffers.G || regs.clear_buffers.B ||
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regs.clear_buffers.A;
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const bool use_depth = regs.clear_buffers.Z;
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const bool use_stencil = regs.clear_buffers.S;
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if (!use_color && !use_depth && !use_stencil) {
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return;
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}
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std::scoped_lock lock{texture_cache.mutex};
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texture_cache.UpdateRenderTargets(true);
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const Framebuffer* const framebuffer = texture_cache.GetFramebuffer();
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const VkExtent2D render_area = framebuffer->RenderArea();
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scheduler.RequestRenderpass(framebuffer);
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u32 up_scale = 1;
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u32 down_shift = 0;
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if (texture_cache.IsRescaling()) {
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up_scale = Settings::values.resolution_info.up_scale;
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down_shift = Settings::values.resolution_info.down_shift;
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}
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UpdateViewportsState(regs);
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VkClearRect clear_rect{
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.rect = GetScissorState(regs, 0, up_scale, down_shift),
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.baseArrayLayer = regs.clear_buffers.layer,
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.layerCount = 1,
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};
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if (clear_rect.rect.extent.width == 0 || clear_rect.rect.extent.height == 0) {
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return;
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}
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clear_rect.rect.extent = VkExtent2D{
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.width = std::min(clear_rect.rect.extent.width, render_area.width),
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.height = std::min(clear_rect.rect.extent.height, render_area.height),
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};
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const u32 color_attachment = regs.clear_buffers.RT;
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if (use_color && framebuffer->HasAspectColorBit(color_attachment)) {
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VkClearValue clear_value;
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bool is_integer = false;
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bool is_signed = false;
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size_t int_size = 8;
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for (std::size_t i = 0; i < Tegra::Engines::Maxwell3D::Regs::NumRenderTargets; ++i) {
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const auto& this_rt = regs.rt[i];
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if (this_rt.Address() == 0) {
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continue;
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}
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if (this_rt.format == Tegra::RenderTargetFormat::NONE) {
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continue;
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}
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const auto format =
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VideoCore::Surface::PixelFormatFromRenderTargetFormat(this_rt.format);
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is_integer = IsPixelFormatInteger(format);
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is_signed = IsPixelFormatSignedInteger(format);
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int_size = PixelComponentSizeBitsInteger(format);
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break;
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}
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if (!is_integer) {
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std::memcpy(clear_value.color.float32, regs.clear_color, sizeof(regs.clear_color));
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} else if (!is_signed) {
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for (size_t i = 0; i < 4; i++) {
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clear_value.color.uint32[i] = static_cast<u32>(
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static_cast<f32>(static_cast<u64>(int_size) << 1U) * regs.clear_color[i]);
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}
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} else {
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for (size_t i = 0; i < 4; i++) {
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clear_value.color.int32[i] =
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static_cast<s32>(static_cast<f32>(static_cast<s64>(int_size - 1) << 1) *
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(regs.clear_color[i] - 0.5f));
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}
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}
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scheduler.Record([color_attachment, clear_value, clear_rect](vk::CommandBuffer cmdbuf) {
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const VkClearAttachment attachment{
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.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
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.colorAttachment = color_attachment,
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.clearValue = clear_value,
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};
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cmdbuf.ClearAttachments(attachment, clear_rect);
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});
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}
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if (!use_depth && !use_stencil) {
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return;
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}
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VkImageAspectFlags aspect_flags = 0;
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if (use_depth && framebuffer->HasAspectDepthBit()) {
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aspect_flags |= VK_IMAGE_ASPECT_DEPTH_BIT;
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}
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if (use_stencil && framebuffer->HasAspectStencilBit()) {
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aspect_flags |= VK_IMAGE_ASPECT_STENCIL_BIT;
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}
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if (aspect_flags == 0) {
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return;
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}
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scheduler.Record([clear_depth = regs.clear_depth, clear_stencil = regs.clear_stencil,
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clear_rect, aspect_flags](vk::CommandBuffer cmdbuf) {
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VkClearAttachment attachment;
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attachment.aspectMask = aspect_flags;
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attachment.colorAttachment = 0;
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attachment.clearValue.depthStencil.depth = clear_depth;
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attachment.clearValue.depthStencil.stencil = clear_stencil;
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cmdbuf.ClearAttachments(attachment, clear_rect);
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});
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}
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void RasterizerVulkan::DispatchCompute() {
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FlushWork();
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ComputePipeline* const pipeline{pipeline_cache.CurrentComputePipeline()};
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if (!pipeline) {
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return;
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}
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std::scoped_lock lock{texture_cache.mutex, buffer_cache.mutex};
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pipeline->Configure(kepler_compute, gpu_memory, scheduler, buffer_cache, texture_cache);
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const auto& qmd{kepler_compute.launch_description};
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const std::array<u32, 3> dim{qmd.grid_dim_x, qmd.grid_dim_y, qmd.grid_dim_z};
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([dim](vk::CommandBuffer cmdbuf) { cmdbuf.Dispatch(dim[0], dim[1], dim[2]); });
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}
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void RasterizerVulkan::ResetCounter(VideoCore::QueryType type) {
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query_cache.ResetCounter(type);
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}
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void RasterizerVulkan::Query(GPUVAddr gpu_addr, VideoCore::QueryType type,
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std::optional<u64> timestamp) {
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query_cache.Query(gpu_addr, type, timestamp);
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}
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void RasterizerVulkan::BindGraphicsUniformBuffer(size_t stage, u32 index, GPUVAddr gpu_addr,
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u32 size) {
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buffer_cache.BindGraphicsUniformBuffer(stage, index, gpu_addr, size);
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}
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void Vulkan::RasterizerVulkan::DisableGraphicsUniformBuffer(size_t stage, u32 index) {
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buffer_cache.DisableGraphicsUniformBuffer(stage, index);
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}
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void RasterizerVulkan::FlushAll() {}
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void RasterizerVulkan::FlushRegion(VAddr addr, u64 size) {
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if (addr == 0 || size == 0) {
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return;
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}
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{
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std::scoped_lock lock{texture_cache.mutex};
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texture_cache.DownloadMemory(addr, size);
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}
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{
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std::scoped_lock lock{buffer_cache.mutex};
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buffer_cache.DownloadMemory(addr, size);
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}
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query_cache.FlushRegion(addr, size);
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}
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bool RasterizerVulkan::MustFlushRegion(VAddr addr, u64 size) {
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std::scoped_lock lock{texture_cache.mutex, buffer_cache.mutex};
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if (!Settings::IsGPULevelHigh()) {
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return buffer_cache.IsRegionGpuModified(addr, size);
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}
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return texture_cache.IsRegionGpuModified(addr, size) ||
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buffer_cache.IsRegionGpuModified(addr, size);
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}
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void RasterizerVulkan::InvalidateRegion(VAddr addr, u64 size) {
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if (addr == 0 || size == 0) {
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return;
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}
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{
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std::scoped_lock lock{texture_cache.mutex};
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texture_cache.WriteMemory(addr, size);
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}
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{
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std::scoped_lock lock{buffer_cache.mutex};
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buffer_cache.WriteMemory(addr, size);
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}
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pipeline_cache.InvalidateRegion(addr, size);
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query_cache.InvalidateRegion(addr, size);
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}
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void RasterizerVulkan::OnCPUWrite(VAddr addr, u64 size) {
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if (addr == 0 || size == 0) {
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return;
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}
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pipeline_cache.OnCPUWrite(addr, size);
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{
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std::scoped_lock lock{texture_cache.mutex};
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texture_cache.WriteMemory(addr, size);
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}
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{
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std::scoped_lock lock{buffer_cache.mutex};
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buffer_cache.CachedWriteMemory(addr, size);
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}
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}
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void RasterizerVulkan::SyncGuestHost() {
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pipeline_cache.SyncGuestHost();
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{
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std::scoped_lock lock{buffer_cache.mutex};
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buffer_cache.FlushCachedWrites();
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}
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}
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void RasterizerVulkan::UnmapMemory(VAddr addr, u64 size) {
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{
|
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std::scoped_lock lock{texture_cache.mutex};
|
|
texture_cache.UnmapMemory(addr, size);
|
|
}
|
|
{
|
|
std::scoped_lock lock{buffer_cache.mutex};
|
|
buffer_cache.WriteMemory(addr, size);
|
|
}
|
|
pipeline_cache.OnCPUWrite(addr, size);
|
|
}
|
|
|
|
void RasterizerVulkan::ModifyGPUMemory(GPUVAddr addr, u64 size) {
|
|
{
|
|
std::scoped_lock lock{texture_cache.mutex};
|
|
texture_cache.UnmapGPUMemory(addr, size);
|
|
}
|
|
}
|
|
|
|
void RasterizerVulkan::SignalSemaphore(GPUVAddr addr, u32 value) {
|
|
if (!gpu.IsAsync()) {
|
|
gpu_memory.Write<u32>(addr, value);
|
|
return;
|
|
}
|
|
fence_manager.SignalSemaphore(addr, value);
|
|
}
|
|
|
|
void RasterizerVulkan::SignalSyncPoint(u32 value) {
|
|
if (!gpu.IsAsync()) {
|
|
gpu.IncrementSyncPoint(value);
|
|
return;
|
|
}
|
|
fence_manager.SignalSyncPoint(value);
|
|
}
|
|
|
|
void RasterizerVulkan::SignalReference() {
|
|
if (!gpu.IsAsync()) {
|
|
return;
|
|
}
|
|
fence_manager.SignalOrdering();
|
|
}
|
|
|
|
void RasterizerVulkan::ReleaseFences() {
|
|
if (!gpu.IsAsync()) {
|
|
return;
|
|
}
|
|
fence_manager.WaitPendingFences();
|
|
}
|
|
|
|
void RasterizerVulkan::FlushAndInvalidateRegion(VAddr addr, u64 size) {
|
|
if (Settings::IsGPULevelExtreme()) {
|
|
FlushRegion(addr, size);
|
|
}
|
|
InvalidateRegion(addr, size);
|
|
}
|
|
|
|
void RasterizerVulkan::WaitForIdle() {
|
|
// Everything but wait pixel operations. This intentionally includes FRAGMENT_SHADER_BIT because
|
|
// fragment shaders can still write storage buffers.
|
|
VkPipelineStageFlags flags =
|
|
VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT | VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
|
|
VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
|
|
VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
|
|
VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
|
|
VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | VK_PIPELINE_STAGE_TRANSFER_BIT;
|
|
if (device.IsExtTransformFeedbackSupported()) {
|
|
flags |= VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT;
|
|
}
|
|
|
|
scheduler.RequestOutsideRenderPassOperationContext();
|
|
scheduler.Record([event = *wfi_event, flags](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetEvent(event, flags);
|
|
cmdbuf.WaitEvents(event, flags, VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, {}, {}, {});
|
|
});
|
|
SignalReference();
|
|
}
|
|
|
|
void RasterizerVulkan::FragmentBarrier() {
|
|
// We already put barriers when a render pass finishes
|
|
scheduler.RequestOutsideRenderPassOperationContext();
|
|
}
|
|
|
|
void RasterizerVulkan::TiledCacheBarrier() {
|
|
// TODO: Implementing tiled barriers requires rewriting a good chunk of the Vulkan backend
|
|
}
|
|
|
|
void RasterizerVulkan::FlushCommands() {
|
|
if (draw_counter == 0) {
|
|
return;
|
|
}
|
|
draw_counter = 0;
|
|
scheduler.Flush();
|
|
}
|
|
|
|
void RasterizerVulkan::TickFrame() {
|
|
draw_counter = 0;
|
|
update_descriptor_queue.TickFrame();
|
|
fence_manager.TickFrame();
|
|
staging_pool.TickFrame();
|
|
{
|
|
std::scoped_lock lock{texture_cache.mutex};
|
|
texture_cache.TickFrame();
|
|
}
|
|
{
|
|
std::scoped_lock lock{buffer_cache.mutex};
|
|
buffer_cache.TickFrame();
|
|
}
|
|
}
|
|
|
|
bool RasterizerVulkan::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src,
|
|
const Tegra::Engines::Fermi2D::Surface& dst,
|
|
const Tegra::Engines::Fermi2D::Config& copy_config) {
|
|
std::scoped_lock lock{texture_cache.mutex};
|
|
texture_cache.BlitImage(dst, src, copy_config);
|
|
return true;
|
|
}
|
|
|
|
Tegra::Engines::AccelerateDMAInterface& RasterizerVulkan::AccessAccelerateDMA() {
|
|
return accelerate_dma;
|
|
}
|
|
|
|
void RasterizerVulkan::AccelerateInlineToMemory(GPUVAddr address, size_t copy_size,
|
|
std::span<u8> memory) {
|
|
auto cpu_addr = gpu_memory.GpuToCpuAddress(address);
|
|
if (!cpu_addr) [[unlikely]] {
|
|
gpu_memory.WriteBlock(address, memory.data(), copy_size);
|
|
return;
|
|
}
|
|
gpu_memory.WriteBlockUnsafe(address, memory.data(), copy_size);
|
|
{
|
|
std::unique_lock<std::mutex> lock{buffer_cache.mutex};
|
|
if (!buffer_cache.InlineMemory(*cpu_addr, copy_size, memory)) {
|
|
buffer_cache.WriteMemory(*cpu_addr, copy_size);
|
|
}
|
|
}
|
|
{
|
|
std::scoped_lock lock_texture{texture_cache.mutex};
|
|
texture_cache.WriteMemory(*cpu_addr, copy_size);
|
|
}
|
|
pipeline_cache.InvalidateRegion(*cpu_addr, copy_size);
|
|
query_cache.InvalidateRegion(*cpu_addr, copy_size);
|
|
}
|
|
|
|
bool RasterizerVulkan::AccelerateDisplay(const Tegra::FramebufferConfig& config,
|
|
VAddr framebuffer_addr, u32 pixel_stride) {
|
|
if (!framebuffer_addr) {
|
|
return false;
|
|
}
|
|
std::scoped_lock lock{texture_cache.mutex};
|
|
ImageView* const image_view = texture_cache.TryFindFramebufferImageView(framebuffer_addr);
|
|
if (!image_view) {
|
|
return false;
|
|
}
|
|
screen_info.image_view = image_view->Handle(Shader::TextureType::Color2D);
|
|
screen_info.width = image_view->size.width;
|
|
screen_info.height = image_view->size.height;
|
|
screen_info.is_srgb = VideoCore::Surface::IsPixelFormatSRGB(image_view->format);
|
|
return true;
|
|
}
|
|
|
|
void RasterizerVulkan::LoadDiskResources(u64 title_id, std::stop_token stop_loading,
|
|
const VideoCore::DiskResourceLoadCallback& callback) {
|
|
pipeline_cache.LoadDiskResources(title_id, stop_loading, callback);
|
|
}
|
|
|
|
void RasterizerVulkan::FlushWork() {
|
|
static constexpr u32 DRAWS_TO_DISPATCH = 4096;
|
|
|
|
// Only check multiples of 8 draws
|
|
static_assert(DRAWS_TO_DISPATCH % 8 == 0);
|
|
if ((++draw_counter & 7) != 7) {
|
|
return;
|
|
}
|
|
if (draw_counter < DRAWS_TO_DISPATCH) {
|
|
// Send recorded tasks to the worker thread
|
|
scheduler.DispatchWork();
|
|
return;
|
|
}
|
|
// Otherwise (every certain number of draws) flush execution.
|
|
// This submits commands to the Vulkan driver.
|
|
scheduler.Flush();
|
|
draw_counter = 0;
|
|
}
|
|
|
|
AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
|
|
|
|
bool AccelerateDMA::BufferClear(GPUVAddr src_address, u64 amount, u32 value) {
|
|
std::scoped_lock lock{buffer_cache.mutex};
|
|
return buffer_cache.DMAClear(src_address, amount, value);
|
|
}
|
|
|
|
bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
|
|
std::scoped_lock lock{buffer_cache.mutex};
|
|
return buffer_cache.DMACopy(src_address, dest_address, amount);
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateDynamicStates() {
|
|
auto& regs = maxwell3d.regs;
|
|
UpdateViewportsState(regs);
|
|
UpdateScissorsState(regs);
|
|
UpdateDepthBias(regs);
|
|
UpdateBlendConstants(regs);
|
|
UpdateDepthBounds(regs);
|
|
UpdateStencilFaces(regs);
|
|
UpdateLineWidth(regs);
|
|
if (device.IsExtExtendedDynamicStateSupported()) {
|
|
UpdateCullMode(regs);
|
|
UpdateDepthBoundsTestEnable(regs);
|
|
UpdateDepthTestEnable(regs);
|
|
UpdateDepthWriteEnable(regs);
|
|
UpdateDepthCompareOp(regs);
|
|
UpdateFrontFace(regs);
|
|
UpdateStencilOp(regs);
|
|
UpdateStencilTestEnable(regs);
|
|
if (device.IsExtVertexInputDynamicStateSupported()) {
|
|
UpdateVertexInput(regs);
|
|
}
|
|
}
|
|
}
|
|
|
|
void RasterizerVulkan::BeginTransformFeedback() {
|
|
const auto& regs = maxwell3d.regs;
|
|
if (regs.tfb_enabled == 0) {
|
|
return;
|
|
}
|
|
if (!device.IsExtTransformFeedbackSupported()) {
|
|
LOG_ERROR(Render_Vulkan, "Transform feedbacks used but not supported");
|
|
return;
|
|
}
|
|
UNIMPLEMENTED_IF(regs.IsShaderConfigEnabled(Maxwell::ShaderProgram::TesselationControl) ||
|
|
regs.IsShaderConfigEnabled(Maxwell::ShaderProgram::TesselationEval) ||
|
|
regs.IsShaderConfigEnabled(Maxwell::ShaderProgram::Geometry));
|
|
scheduler.Record(
|
|
[](vk::CommandBuffer cmdbuf) { cmdbuf.BeginTransformFeedbackEXT(0, 0, nullptr, nullptr); });
|
|
}
|
|
|
|
void RasterizerVulkan::EndTransformFeedback() {
|
|
const auto& regs = maxwell3d.regs;
|
|
if (regs.tfb_enabled == 0) {
|
|
return;
|
|
}
|
|
if (!device.IsExtTransformFeedbackSupported()) {
|
|
return;
|
|
}
|
|
scheduler.Record(
|
|
[](vk::CommandBuffer cmdbuf) { cmdbuf.EndTransformFeedbackEXT(0, 0, nullptr, nullptr); });
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateViewportsState(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchViewports()) {
|
|
return;
|
|
}
|
|
const bool is_rescaling{texture_cache.IsRescaling()};
|
|
const float scale = is_rescaling ? Settings::values.resolution_info.up_factor : 1.0f;
|
|
const std::array viewports{
|
|
GetViewportState(device, regs, 0, scale), GetViewportState(device, regs, 1, scale),
|
|
GetViewportState(device, regs, 2, scale), GetViewportState(device, regs, 3, scale),
|
|
GetViewportState(device, regs, 4, scale), GetViewportState(device, regs, 5, scale),
|
|
GetViewportState(device, regs, 6, scale), GetViewportState(device, regs, 7, scale),
|
|
GetViewportState(device, regs, 8, scale), GetViewportState(device, regs, 9, scale),
|
|
GetViewportState(device, regs, 10, scale), GetViewportState(device, regs, 11, scale),
|
|
GetViewportState(device, regs, 12, scale), GetViewportState(device, regs, 13, scale),
|
|
GetViewportState(device, regs, 14, scale), GetViewportState(device, regs, 15, scale),
|
|
};
|
|
scheduler.Record([viewports](vk::CommandBuffer cmdbuf) { cmdbuf.SetViewport(0, viewports); });
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateScissorsState(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchScissors()) {
|
|
return;
|
|
}
|
|
u32 up_scale = 1;
|
|
u32 down_shift = 0;
|
|
if (texture_cache.IsRescaling()) {
|
|
up_scale = Settings::values.resolution_info.up_scale;
|
|
down_shift = Settings::values.resolution_info.down_shift;
|
|
}
|
|
const std::array scissors{
|
|
GetScissorState(regs, 0, up_scale, down_shift),
|
|
GetScissorState(regs, 1, up_scale, down_shift),
|
|
GetScissorState(regs, 2, up_scale, down_shift),
|
|
GetScissorState(regs, 3, up_scale, down_shift),
|
|
GetScissorState(regs, 4, up_scale, down_shift),
|
|
GetScissorState(regs, 5, up_scale, down_shift),
|
|
GetScissorState(regs, 6, up_scale, down_shift),
|
|
GetScissorState(regs, 7, up_scale, down_shift),
|
|
GetScissorState(regs, 8, up_scale, down_shift),
|
|
GetScissorState(regs, 9, up_scale, down_shift),
|
|
GetScissorState(regs, 10, up_scale, down_shift),
|
|
GetScissorState(regs, 11, up_scale, down_shift),
|
|
GetScissorState(regs, 12, up_scale, down_shift),
|
|
GetScissorState(regs, 13, up_scale, down_shift),
|
|
GetScissorState(regs, 14, up_scale, down_shift),
|
|
GetScissorState(regs, 15, up_scale, down_shift),
|
|
};
|
|
scheduler.Record([scissors](vk::CommandBuffer cmdbuf) { cmdbuf.SetScissor(0, scissors); });
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateDepthBias(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchDepthBias()) {
|
|
return;
|
|
}
|
|
float units = regs.polygon_offset_units / 2.0f;
|
|
const bool is_d24 = regs.zeta.format == Tegra::DepthFormat::S8_UINT_Z24_UNORM ||
|
|
regs.zeta.format == Tegra::DepthFormat::D24X8_UNORM ||
|
|
regs.zeta.format == Tegra::DepthFormat::D24S8_UNORM ||
|
|
regs.zeta.format == Tegra::DepthFormat::D24C8_UNORM;
|
|
if (is_d24 && !device.SupportsD24DepthBuffer()) {
|
|
// the base formulas can be obtained from here:
|
|
// https://docs.microsoft.com/en-us/windows/win32/direct3d11/d3d10-graphics-programming-guide-output-merger-stage-depth-bias
|
|
const double rescale_factor =
|
|
static_cast<double>(1ULL << (32 - 24)) / (static_cast<double>(0x1.ep+127));
|
|
units = static_cast<float>(static_cast<double>(units) * rescale_factor);
|
|
}
|
|
scheduler.Record([constant = units, clamp = regs.polygon_offset_clamp,
|
|
factor = regs.polygon_offset_factor](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetDepthBias(constant, clamp, factor);
|
|
});
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateBlendConstants(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchBlendConstants()) {
|
|
return;
|
|
}
|
|
const std::array blend_color = {regs.blend_color.r, regs.blend_color.g, regs.blend_color.b,
|
|
regs.blend_color.a};
|
|
scheduler.Record(
|
|
[blend_color](vk::CommandBuffer cmdbuf) { cmdbuf.SetBlendConstants(blend_color.data()); });
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateDepthBounds(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchDepthBounds()) {
|
|
return;
|
|
}
|
|
scheduler.Record([min = regs.depth_bounds[0], max = regs.depth_bounds[1]](
|
|
vk::CommandBuffer cmdbuf) { cmdbuf.SetDepthBounds(min, max); });
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchStencilProperties()) {
|
|
return;
|
|
}
|
|
if (regs.stencil_two_side_enable) {
|
|
// Separate values per face
|
|
scheduler.Record(
|
|
[front_ref = regs.stencil_front_func_ref, front_write_mask = regs.stencil_front_mask,
|
|
front_test_mask = regs.stencil_front_func_mask, back_ref = regs.stencil_back_func_ref,
|
|
back_write_mask = regs.stencil_back_mask,
|
|
back_test_mask = regs.stencil_back_func_mask](vk::CommandBuffer cmdbuf) {
|
|
// Front face
|
|
cmdbuf.SetStencilReference(VK_STENCIL_FACE_FRONT_BIT, front_ref);
|
|
cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_FRONT_BIT, front_write_mask);
|
|
cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_FRONT_BIT, front_test_mask);
|
|
|
|
// Back face
|
|
cmdbuf.SetStencilReference(VK_STENCIL_FACE_BACK_BIT, back_ref);
|
|
cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_BACK_BIT, back_write_mask);
|
|
cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_BACK_BIT, back_test_mask);
|
|
});
|
|
} else {
|
|
// Front face defines both faces
|
|
scheduler.Record([ref = regs.stencil_back_func_ref, write_mask = regs.stencil_back_mask,
|
|
test_mask = regs.stencil_back_func_mask](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetStencilReference(VK_STENCIL_FACE_FRONT_AND_BACK, ref);
|
|
cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_FRONT_AND_BACK, write_mask);
|
|
cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_FRONT_AND_BACK, test_mask);
|
|
});
|
|
}
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateLineWidth(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchLineWidth()) {
|
|
return;
|
|
}
|
|
const float width = regs.line_smooth_enable ? regs.line_width_smooth : regs.line_width_aliased;
|
|
scheduler.Record([width](vk::CommandBuffer cmdbuf) { cmdbuf.SetLineWidth(width); });
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateCullMode(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchCullMode()) {
|
|
return;
|
|
}
|
|
scheduler.Record(
|
|
[enabled = regs.cull_test_enabled, cull_face = regs.cull_face](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetCullModeEXT(enabled ? MaxwellToVK::CullFace(cull_face) : VK_CULL_MODE_NONE);
|
|
});
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateDepthBoundsTestEnable(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchDepthBoundsTestEnable()) {
|
|
return;
|
|
}
|
|
bool enabled = regs.depth_bounds_enable;
|
|
if (enabled && !device.IsDepthBoundsSupported()) {
|
|
LOG_WARNING(Render_Vulkan, "Depth bounds is enabled but not supported");
|
|
enabled = false;
|
|
}
|
|
scheduler.Record([enable = regs.depth_bounds_enable](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetDepthBoundsTestEnableEXT(enable);
|
|
});
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateDepthTestEnable(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchDepthTestEnable()) {
|
|
return;
|
|
}
|
|
scheduler.Record([enable = regs.depth_test_enable](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetDepthTestEnableEXT(enable);
|
|
});
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateDepthWriteEnable(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchDepthWriteEnable()) {
|
|
return;
|
|
}
|
|
scheduler.Record([enable = regs.depth_write_enabled](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetDepthWriteEnableEXT(enable);
|
|
});
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateDepthCompareOp(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchDepthCompareOp()) {
|
|
return;
|
|
}
|
|
scheduler.Record([func = regs.depth_test_func](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetDepthCompareOpEXT(MaxwellToVK::ComparisonOp(func));
|
|
});
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchFrontFace()) {
|
|
return;
|
|
}
|
|
|
|
VkFrontFace front_face = MaxwellToVK::FrontFace(regs.front_face);
|
|
if (regs.screen_y_control.triangle_rast_flip != 0) {
|
|
front_face = front_face == VK_FRONT_FACE_CLOCKWISE ? VK_FRONT_FACE_COUNTER_CLOCKWISE
|
|
: VK_FRONT_FACE_CLOCKWISE;
|
|
}
|
|
scheduler.Record(
|
|
[front_face](vk::CommandBuffer cmdbuf) { cmdbuf.SetFrontFaceEXT(front_face); });
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchStencilOp()) {
|
|
return;
|
|
}
|
|
const Maxwell::StencilOp fail = regs.stencil_front_op_fail;
|
|
const Maxwell::StencilOp zfail = regs.stencil_front_op_zfail;
|
|
const Maxwell::StencilOp zpass = regs.stencil_front_op_zpass;
|
|
const Maxwell::ComparisonOp compare = regs.stencil_front_func_func;
|
|
if (regs.stencil_two_side_enable) {
|
|
// Separate stencil op per face
|
|
const Maxwell::StencilOp back_fail = regs.stencil_back_op_fail;
|
|
const Maxwell::StencilOp back_zfail = regs.stencil_back_op_zfail;
|
|
const Maxwell::StencilOp back_zpass = regs.stencil_back_op_zpass;
|
|
const Maxwell::ComparisonOp back_compare = regs.stencil_back_func_func;
|
|
scheduler.Record([fail, zfail, zpass, compare, back_fail, back_zfail, back_zpass,
|
|
back_compare](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetStencilOpEXT(VK_STENCIL_FACE_FRONT_BIT, MaxwellToVK::StencilOp(fail),
|
|
MaxwellToVK::StencilOp(zpass), MaxwellToVK::StencilOp(zfail),
|
|
MaxwellToVK::ComparisonOp(compare));
|
|
cmdbuf.SetStencilOpEXT(VK_STENCIL_FACE_BACK_BIT, MaxwellToVK::StencilOp(back_fail),
|
|
MaxwellToVK::StencilOp(back_zpass),
|
|
MaxwellToVK::StencilOp(back_zfail),
|
|
MaxwellToVK::ComparisonOp(back_compare));
|
|
});
|
|
} else {
|
|
// Front face defines the stencil op of both faces
|
|
scheduler.Record([fail, zfail, zpass, compare](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetStencilOpEXT(VK_STENCIL_FACE_FRONT_AND_BACK, MaxwellToVK::StencilOp(fail),
|
|
MaxwellToVK::StencilOp(zpass), MaxwellToVK::StencilOp(zfail),
|
|
MaxwellToVK::ComparisonOp(compare));
|
|
});
|
|
}
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
if (!state_tracker.TouchStencilTestEnable()) {
|
|
return;
|
|
}
|
|
scheduler.Record([enable = regs.stencil_enable](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetStencilTestEnableEXT(enable);
|
|
});
|
|
}
|
|
|
|
void RasterizerVulkan::UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs) {
|
|
auto& dirty{maxwell3d.dirty.flags};
|
|
if (!dirty[Dirty::VertexInput]) {
|
|
return;
|
|
}
|
|
dirty[Dirty::VertexInput] = false;
|
|
|
|
boost::container::static_vector<VkVertexInputBindingDescription2EXT, 32> bindings;
|
|
boost::container::static_vector<VkVertexInputAttributeDescription2EXT, 32> attributes;
|
|
|
|
// There seems to be a bug on Nvidia's driver where updating only higher attributes ends up
|
|
// generating dirty state. Track the highest dirty attribute and update all attributes until
|
|
// that one.
|
|
size_t highest_dirty_attr{};
|
|
for (size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) {
|
|
if (dirty[Dirty::VertexAttribute0 + index]) {
|
|
highest_dirty_attr = index;
|
|
}
|
|
}
|
|
for (size_t index = 0; index < highest_dirty_attr; ++index) {
|
|
const Maxwell::VertexAttribute attribute{regs.vertex_attrib_format[index]};
|
|
const u32 binding{attribute.buffer};
|
|
dirty[Dirty::VertexAttribute0 + index] = false;
|
|
dirty[Dirty::VertexBinding0 + static_cast<size_t>(binding)] = true;
|
|
if (!attribute.constant) {
|
|
attributes.push_back({
|
|
.sType = VK_STRUCTURE_TYPE_VERTEX_INPUT_ATTRIBUTE_DESCRIPTION_2_EXT,
|
|
.pNext = nullptr,
|
|
.location = static_cast<u32>(index),
|
|
.binding = binding,
|
|
.format = MaxwellToVK::VertexFormat(attribute.type, attribute.size),
|
|
.offset = attribute.offset,
|
|
});
|
|
}
|
|
}
|
|
for (size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) {
|
|
if (!dirty[Dirty::VertexBinding0 + index]) {
|
|
continue;
|
|
}
|
|
dirty[Dirty::VertexBinding0 + index] = false;
|
|
|
|
const u32 binding{static_cast<u32>(index)};
|
|
const auto& input_binding{regs.vertex_array[binding]};
|
|
const bool is_instanced{regs.instanced_arrays.IsInstancingEnabled(binding)};
|
|
bindings.push_back({
|
|
.sType = VK_STRUCTURE_TYPE_VERTEX_INPUT_BINDING_DESCRIPTION_2_EXT,
|
|
.pNext = nullptr,
|
|
.binding = binding,
|
|
.stride = input_binding.stride,
|
|
.inputRate = is_instanced ? VK_VERTEX_INPUT_RATE_INSTANCE : VK_VERTEX_INPUT_RATE_VERTEX,
|
|
.divisor = is_instanced ? input_binding.divisor : 1,
|
|
});
|
|
}
|
|
scheduler.Record([bindings, attributes](vk::CommandBuffer cmdbuf) {
|
|
cmdbuf.SetVertexInputEXT(bindings, attributes);
|
|
});
|
|
}
|
|
|
|
} // namespace Vulkan
|