forked from suyu/suyu
60926ac16b
This is more accurate in terms of describing what the functions are actually doing. Temporal relates to time, not the setting of a temporary itself.
321 lines
13 KiB
C++
321 lines
13 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <vector>
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#include <fmt/format.h>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Attribute;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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namespace {
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u32 GetUniformTypeElementsCount(Tegra::Shader::UniformType uniform_type) {
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switch (uniform_type) {
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case Tegra::Shader::UniformType::Single:
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return 1;
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case Tegra::Shader::UniformType::Double:
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return 2;
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case Tegra::Shader::UniformType::Quad:
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case Tegra::Shader::UniformType::UnsignedQuad:
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return 4;
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default:
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UNIMPLEMENTED_MSG("Unimplemented size={}!", static_cast<u32>(uniform_type));
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return 1;
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}
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}
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} // namespace
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u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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switch (opcode->get().GetId()) {
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case OpCode::Id::LD_A: {
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// Note: Shouldn't this be interp mode flat? As in no interpolation made.
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UNIMPLEMENTED_IF_MSG(instr.gpr8.Value() != Register::ZeroIndex,
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"Indirect attribute loads are not supported");
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UNIMPLEMENTED_IF_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) != 0,
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"Unaligned attribute loads are not supported");
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UNIMPLEMENTED_IF_MSG(instr.attribute.fmt20.IsPhysical() &&
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instr.attribute.fmt20.size != Tegra::Shader::AttributeSize::Word,
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"Non-32 bits PHYS reads are not implemented");
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const Node buffer{GetRegister(instr.gpr39)};
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u64 next_element = instr.attribute.fmt20.element;
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auto next_index = static_cast<u64>(instr.attribute.fmt20.index.Value());
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const auto LoadNextElement = [&](u32 reg_offset) {
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const Node attribute{instr.attribute.fmt20.IsPhysical()
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? GetPhysicalInputAttribute(instr.gpr8, buffer)
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: GetInputAttribute(static_cast<Attribute::Index>(next_index),
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next_element, buffer)};
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SetRegister(bb, instr.gpr0.Value() + reg_offset, attribute);
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// Load the next attribute element into the following register. If the element
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// to load goes beyond the vec4 size, load the first element of the next
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// attribute.
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next_element = (next_element + 1) % 4;
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next_index = next_index + (next_element == 0 ? 1 : 0);
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};
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
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LoadNextElement(reg_offset);
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}
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break;
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}
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case OpCode::Id::LD_C: {
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UNIMPLEMENTED_IF(instr.ld_c.unknown != 0);
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Node index = GetRegister(instr.gpr8);
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const Node op_a =
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 0, index);
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switch (instr.ld_c.type.Value()) {
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case Tegra::Shader::UniformType::Single:
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SetRegister(bb, instr.gpr0, op_a);
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break;
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case Tegra::Shader::UniformType::Double: {
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const Node op_b =
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 4, index);
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SetTemporary(bb, 0, op_a);
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SetTemporary(bb, 1, op_b);
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SetRegister(bb, instr.gpr0, GetTemporary(0));
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SetRegister(bb, instr.gpr0.Value() + 1, GetTemporary(1));
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled type: {}", static_cast<unsigned>(instr.ld_c.type.Value()));
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}
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break;
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}
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case OpCode::Id::LD_L: {
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LOG_DEBUG(HW_GPU, "LD_L cache management mode: {}",
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static_cast<u64>(instr.ld_l.unknown.Value()));
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const auto GetLmem = [&](s32 offset) {
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ASSERT(offset % 4 == 0);
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const Node immediate_offset = Immediate(static_cast<s32>(instr.smem_imm) + offset);
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const Node address = Operation(OperationCode::IAdd, NO_PRECISE, GetRegister(instr.gpr8),
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immediate_offset);
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return GetLocalMemory(address);
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};
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switch (instr.ldst_sl.type.Value()) {
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case Tegra::Shader::StoreType::Bits32:
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case Tegra::Shader::StoreType::Bits64:
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case Tegra::Shader::StoreType::Bits128: {
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const u32 count = [&]() {
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switch (instr.ldst_sl.type.Value()) {
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case Tegra::Shader::StoreType::Bits32:
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return 1;
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case Tegra::Shader::StoreType::Bits64:
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return 2;
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case Tegra::Shader::StoreType::Bits128:
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return 4;
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default:
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UNREACHABLE();
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return 0;
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}
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}();
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for (u32 i = 0; i < count; ++i)
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SetTemporary(bb, i, GetLmem(i * 4));
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for (u32 i = 0; i < count; ++i)
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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break;
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}
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default:
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UNIMPLEMENTED_MSG("LD_L Unhandled type: {}",
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static_cast<u32>(instr.ldst_sl.type.Value()));
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}
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break;
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}
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case OpCode::Id::LD:
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case OpCode::Id::LDG: {
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const auto type = [instr, &opcode]() -> Tegra::Shader::UniformType {
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switch (opcode->get().GetId()) {
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case OpCode::Id::LD:
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UNIMPLEMENTED_IF_MSG(!instr.generic.extended, "Unextended LD is not implemented");
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return instr.generic.type;
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case OpCode::Id::LDG:
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return instr.ldg.type;
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default:
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UNREACHABLE();
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return {};
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}
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}();
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const auto [real_address_base, base_address, descriptor] =
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TrackAndGetGlobalMemory(bb, instr, false);
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const u32 count = GetUniformTypeElementsCount(type);
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for (u32 i = 0; i < count; ++i) {
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const Node it_offset = Immediate(i * 4);
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const Node real_address =
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Operation(OperationCode::UAdd, NO_PRECISE, real_address_base, it_offset);
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const Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
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SetTemporary(bb, i, gmem);
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}
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for (u32 i = 0; i < count; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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}
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break;
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}
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case OpCode::Id::ST_A: {
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UNIMPLEMENTED_IF_MSG(instr.gpr8.Value() != Register::ZeroIndex,
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"Indirect attribute loads are not supported");
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UNIMPLEMENTED_IF_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) != 0,
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"Unaligned attribute loads are not supported");
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u64 next_element = instr.attribute.fmt20.element;
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auto next_index = static_cast<u64>(instr.attribute.fmt20.index.Value());
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const auto StoreNextElement = [&](u32 reg_offset) {
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const auto dest = GetOutputAttribute(static_cast<Attribute::Index>(next_index),
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next_element, GetRegister(instr.gpr39));
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const auto src = GetRegister(instr.gpr0.Value() + reg_offset);
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bb.push_back(Operation(OperationCode::Assign, dest, src));
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// Load the next attribute element into the following register. If the element
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// to load goes beyond the vec4 size, load the first element of the next
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// attribute.
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next_element = (next_element + 1) % 4;
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next_index = next_index + (next_element == 0 ? 1 : 0);
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};
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
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StoreNextElement(reg_offset);
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}
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break;
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}
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case OpCode::Id::ST_L: {
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LOG_DEBUG(HW_GPU, "ST_L cache management mode: {}",
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static_cast<u64>(instr.st_l.cache_management.Value()));
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const auto GetLmemAddr = [&](s32 offset) {
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ASSERT(offset % 4 == 0);
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const Node immediate = Immediate(static_cast<s32>(instr.smem_imm) + offset);
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return Operation(OperationCode::IAdd, NO_PRECISE, GetRegister(instr.gpr8), immediate);
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};
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switch (instr.ldst_sl.type.Value()) {
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case Tegra::Shader::StoreType::Bits128:
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SetLocalMemory(bb, GetLmemAddr(12), GetRegister(instr.gpr0.Value() + 3));
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SetLocalMemory(bb, GetLmemAddr(8), GetRegister(instr.gpr0.Value() + 2));
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case Tegra::Shader::StoreType::Bits64:
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SetLocalMemory(bb, GetLmemAddr(4), GetRegister(instr.gpr0.Value() + 1));
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case Tegra::Shader::StoreType::Bits32:
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SetLocalMemory(bb, GetLmemAddr(0), GetRegister(instr.gpr0));
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break;
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default:
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UNIMPLEMENTED_MSG("ST_L Unhandled type: {}",
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static_cast<u32>(instr.ldst_sl.type.Value()));
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}
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break;
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}
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case OpCode::Id::ST:
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case OpCode::Id::STG: {
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const auto type = [instr, &opcode]() -> Tegra::Shader::UniformType {
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switch (opcode->get().GetId()) {
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case OpCode::Id::ST:
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UNIMPLEMENTED_IF_MSG(!instr.generic.extended, "Unextended ST is not implemented");
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return instr.generic.type;
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case OpCode::Id::STG:
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return instr.stg.type;
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default:
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UNREACHABLE();
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return {};
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}
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}();
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const auto [real_address_base, base_address, descriptor] =
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TrackAndGetGlobalMemory(bb, instr, true);
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// Encode in temporary registers like this: real_base_address, {registers_to_be_written...}
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SetTemporary(bb, 0, real_address_base);
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const u32 count = GetUniformTypeElementsCount(type);
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for (u32 i = 0; i < count; ++i) {
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SetTemporary(bb, i + 1, GetRegister(instr.gpr0.Value() + i));
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}
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for (u32 i = 0; i < count; ++i) {
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const Node it_offset = Immediate(i * 4);
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const Node real_address =
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Operation(OperationCode::UAdd, NO_PRECISE, real_address_base, it_offset);
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const Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
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bb.push_back(Operation(OperationCode::Assign, gmem, GetTemporary(i + 1)));
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}
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break;
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}
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case OpCode::Id::AL2P: {
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// Ignore al2p.direction since we don't care about it.
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// Calculate emulation fake physical address.
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const Node fixed_address{Immediate(static_cast<u32>(instr.al2p.address))};
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const Node reg{GetRegister(instr.gpr8)};
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const Node fake_address{Operation(OperationCode::IAdd, NO_PRECISE, reg, fixed_address)};
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// Set the fake address to target register.
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SetRegister(bb, instr.gpr0, fake_address);
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// Signal the shader IR to declare all possible attributes and varyings
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uses_physical_attributes = true;
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled memory instruction: {}", opcode->get().GetName());
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}
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return pc;
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}
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std::tuple<Node, Node, GlobalMemoryBase> ShaderIR::TrackAndGetGlobalMemory(NodeBlock& bb,
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Instruction instr,
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bool is_write) {
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const auto addr_register{GetRegister(instr.gmem.gpr)};
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const auto immediate_offset{static_cast<u32>(instr.gmem.offset)};
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const auto [base_address, index, offset] =
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TrackCbuf(addr_register, global_code, static_cast<s64>(global_code.size()));
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ASSERT(base_address != nullptr);
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bb.push_back(Comment(fmt::format("Base address is c[0x{:x}][0x{:x}]", index, offset)));
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const GlobalMemoryBase descriptor{index, offset};
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const auto& [entry, is_new] = used_global_memory.try_emplace(descriptor);
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auto& usage = entry->second;
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if (is_write) {
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usage.is_written = true;
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} else {
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usage.is_read = true;
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}
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const auto real_address =
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Operation(OperationCode::UAdd, NO_PRECISE, Immediate(immediate_offset), addr_register);
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return {real_address, base_address, descriptor};
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}
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} // namespace VideoCommon::Shader
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