forked from suyu/suyu
9764c13d6d
The current texture cache has several points that hurt maintainability and performance. It's easy to break unrelated parts of the cache when doing minor changes. The cache can easily forget valuable information about the cached textures by CPU writes or simply by its normal usage.The current texture cache has several points that hurt maintainability and performance. It's easy to break unrelated parts of the cache when doing minor changes. The cache can easily forget valuable information about the cached textures by CPU writes or simply by its normal usage. This commit aims to address those issues.
127 lines
4.7 KiB
C++
127 lines
4.7 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <bitset>
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "core/core.h"
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#include "video_core/engines/kepler_compute.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/shader_type.h"
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/renderer_base.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines {
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KeplerCompute::KeplerCompute(Core::System& system_, MemoryManager& memory_manager_)
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: system{system_}, memory_manager{memory_manager_}, upload_state{memory_manager, regs.upload} {}
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KeplerCompute::~KeplerCompute() = default;
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void KeplerCompute::BindRasterizer(VideoCore::RasterizerInterface& rasterizer_) {
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rasterizer = &rasterizer_;
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}
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void KeplerCompute::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid KeplerCompute register, increase the size of the Regs structure");
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regs.reg_array[method] = method_argument;
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switch (method) {
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case KEPLER_COMPUTE_REG_INDEX(exec_upload): {
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upload_state.ProcessExec(regs.exec_upload.linear != 0);
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break;
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}
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case KEPLER_COMPUTE_REG_INDEX(data_upload): {
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upload_state.ProcessData(method_argument, is_last_call);
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if (is_last_call) {
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system.GPU().Maxwell3D().OnMemoryWrite();
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}
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break;
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}
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case KEPLER_COMPUTE_REG_INDEX(launch):
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ProcessLaunch();
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break;
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default:
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break;
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}
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}
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void KeplerCompute::CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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u32 methods_pending) {
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for (std::size_t i = 0; i < amount; i++) {
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CallMethod(method, base_start[i], methods_pending - static_cast<u32>(i) <= 1);
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}
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}
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u32 KeplerCompute::AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const {
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ASSERT(stage == ShaderType::Compute);
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const auto& buffer = launch_description.const_buffer_config[const_buffer];
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u32 result;
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std::memcpy(&result, memory_manager.GetPointer(buffer.Address() + offset), sizeof(u32));
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return result;
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}
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SamplerDescriptor KeplerCompute::AccessBoundSampler(ShaderType stage, u64 offset) const {
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return AccessBindlessSampler(stage, regs.tex_cb_index, offset * sizeof(Texture::TextureHandle));
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}
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SamplerDescriptor KeplerCompute::AccessBindlessSampler(ShaderType stage, u64 const_buffer,
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u64 offset) const {
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ASSERT(stage == ShaderType::Compute);
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const auto& tex_info_buffer = launch_description.const_buffer_config[const_buffer];
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const GPUVAddr tex_info_address = tex_info_buffer.Address() + offset;
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return AccessSampler(memory_manager.Read<u32>(tex_info_address));
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}
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SamplerDescriptor KeplerCompute::AccessSampler(u32 handle) const {
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const Texture::TextureHandle tex_handle{handle};
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const Texture::TICEntry tic = GetTICEntry(tex_handle.tic_id);
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const Texture::TSCEntry tsc = GetTSCEntry(tex_handle.tsc_id);
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SamplerDescriptor result = SamplerDescriptor::FromTIC(tic);
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result.is_shadow.Assign(tsc.depth_compare_enabled.Value());
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return result;
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}
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VideoCore::GuestDriverProfile& KeplerCompute::AccessGuestDriverProfile() {
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return rasterizer->AccessGuestDriverProfile();
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}
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const VideoCore::GuestDriverProfile& KeplerCompute::AccessGuestDriverProfile() const {
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return rasterizer->AccessGuestDriverProfile();
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}
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void KeplerCompute::ProcessLaunch() {
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const GPUVAddr launch_desc_loc = regs.launch_desc_loc.Address();
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memory_manager.ReadBlockUnsafe(launch_desc_loc, &launch_description,
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LaunchParams::NUM_LAUNCH_PARAMETERS * sizeof(u32));
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const GPUVAddr code_addr = regs.code_loc.Address() + launch_description.program_start;
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LOG_TRACE(HW_GPU, "Compute invocation launched at address 0x{:016x}", code_addr);
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rasterizer->DispatchCompute(code_addr);
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}
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Texture::TICEntry KeplerCompute::GetTICEntry(u32 tic_index) const {
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const GPUVAddr tic_address_gpu{regs.tic.Address() + tic_index * sizeof(Texture::TICEntry)};
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Texture::TICEntry tic_entry;
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memory_manager.ReadBlockUnsafe(tic_address_gpu, &tic_entry, sizeof(Texture::TICEntry));
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return tic_entry;
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}
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Texture::TSCEntry KeplerCompute::GetTSCEntry(u32 tsc_index) const {
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const GPUVAddr tsc_address_gpu{regs.tsc.Address() + tsc_index * sizeof(Texture::TSCEntry)};
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Texture::TSCEntry tsc_entry;
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memory_manager.ReadBlockUnsafe(tsc_address_gpu, &tsc_entry, sizeof(Texture::TSCEntry));
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return tsc_entry;
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}
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} // namespace Tegra::Engines
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