forked from suyu/suyu
90 lines
2.8 KiB
C++
90 lines
2.8 KiB
C++
// Copyright 2012 Michael Kang, 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <assert.h>
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#include "core/arm/skyeye_common/armdefs.h"
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void switch_mode(arm_core_t *core, uint32_t mode) {
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if (core->Mode == mode)
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return;
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if (mode != USERBANK) {
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switch (core->Mode) {
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case USER32MODE:
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core->Reg_usr[0] = core->Reg[13];
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core->Reg_usr[1] = core->Reg[14];
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break;
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case IRQ32MODE:
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core->Reg_irq[0] = core->Reg[13];
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core->Reg_irq[1] = core->Reg[14];
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core->Spsr[IRQBANK] = core->Spsr_copy;
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break;
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case SVC32MODE:
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core->Reg_svc[0] = core->Reg[13];
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core->Reg_svc[1] = core->Reg[14];
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core->Spsr[SVCBANK] = core->Spsr_copy;
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break;
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case ABORT32MODE:
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core->Reg_abort[0] = core->Reg[13];
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core->Reg_abort[1] = core->Reg[14];
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core->Spsr[ABORTBANK] = core->Spsr_copy;
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break;
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case UNDEF32MODE:
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core->Reg_undef[0] = core->Reg[13];
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core->Reg_undef[1] = core->Reg[14];
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core->Spsr[UNDEFBANK] = core->Spsr_copy;
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break;
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case FIQ32MODE:
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core->Reg_firq[0] = core->Reg[13];
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core->Reg_firq[1] = core->Reg[14];
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core->Spsr[FIQBANK] = core->Spsr_copy;
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break;
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}
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switch (mode) {
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case USER32MODE:
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core->Reg[13] = core->Reg_usr[0];
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core->Reg[14] = core->Reg_usr[1];
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core->Bank = USERBANK;
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break;
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case IRQ32MODE:
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core->Reg[13] = core->Reg_irq[0];
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core->Reg[14] = core->Reg_irq[1];
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core->Spsr_copy = core->Spsr[IRQBANK];
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core->Bank = IRQBANK;
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break;
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case SVC32MODE:
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core->Reg[13] = core->Reg_svc[0];
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core->Reg[14] = core->Reg_svc[1];
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core->Spsr_copy = core->Spsr[SVCBANK];
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core->Bank = SVCBANK;
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break;
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case ABORT32MODE:
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core->Reg[13] = core->Reg_abort[0];
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core->Reg[14] = core->Reg_abort[1];
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core->Spsr_copy = core->Spsr[ABORTBANK];
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core->Bank = ABORTBANK;
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break;
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case UNDEF32MODE:
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core->Reg[13] = core->Reg_undef[0];
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core->Reg[14] = core->Reg_undef[1];
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core->Spsr_copy = core->Spsr[UNDEFBANK];
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core->Bank = UNDEFBANK;
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break;
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case FIQ32MODE:
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core->Reg[13] = core->Reg_firq[0];
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core->Reg[14] = core->Reg_firq[1];
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core->Spsr_copy = core->Spsr[FIQBANK];
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core->Bank = FIQBANK;
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break;
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}
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core->Mode = mode;
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} else {
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LOG_CRITICAL(Core_ARM11, "user mode");
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exit(-2);
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}
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}
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