Commit graph

8 commits

Author SHA1 Message Date
ReinUsesLisp
ca05a13c62 glasm: Catch more register leaks
Add support for null registers. These are used when an instruction has
no usages.

This comes handy when an instruction is only used for its CC value, with
the caveat of having to invalidate all pseudo-instructions before
defining the instruction itself in the register allocator. This commits
changes this.

Workaround a bug on Nvidia's condition codes conditional execution using
branches.
2021-07-22 21:51:33 -04:00
ReinUsesLisp
1ee7f8b943 glasm: Do not alias ConditionRef for now
Immediate condition refs where not handled correctly. Just move the
value for now.
2021-07-22 21:51:32 -04:00
ReinUsesLisp
9bb3e008c9 shader: Read branch conditions from an instruction
Fixes the identity removal pass.
2021-07-22 21:51:32 -04:00
ReinUsesLisp
fb3ba62b3a glasm: Fix aliased bitcasts ref counting 2021-07-22 21:51:31 -04:00
ReinUsesLisp
ad61b47f80 glasm: Add conversion instructions to GLASM 2021-07-22 21:51:31 -04:00
ReinUsesLisp
4502595bc2 glasm: Initial GLASM fp64 support 2021-07-22 21:51:30 -04:00
ReinUsesLisp
9f851e3832 glasm: Implement GLASM fp16 packing and move bitwise insns 2021-07-22 21:51:30 -04:00
ReinUsesLisp
b10cf64c48 glasm: Add GLASM backend infrastructure 2021-07-22 21:51:30 -04:00