2018-01-13 22:22:39 +01:00
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// Copyright 2018 yuzu emulator team
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2018-01-04 06:13:23 +01:00
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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2018-02-14 18:47:48 +01:00
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#include <algorithm>
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2018-01-04 06:13:23 +01:00
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#include <unicorn/arm64.h>
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#include "common/assert.h"
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#include "common/microprofile.h"
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#include "core/arm/unicorn/arm_unicorn.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/hle/kernel/svc.h"
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2018-01-04 19:40:01 +01:00
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// Load Unicorn DLL once on Windows using RAII
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2018-01-16 17:39:07 +01:00
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#ifdef _MSC_VER
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2018-01-04 19:40:01 +01:00
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#include <unicorn_dynload.h>
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struct LoadDll {
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private:
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LoadDll() {
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ASSERT(uc_dyn_load(NULL, 0));
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}
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~LoadDll() {
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ASSERT(uc_dyn_free());
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}
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static LoadDll g_load_dll;
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};
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LoadDll LoadDll::g_load_dll;
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#endif
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2018-01-04 06:13:23 +01:00
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#define CHECKED(expr) \
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do { \
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if (auto _cerr = (expr)) { \
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2018-04-27 13:54:05 +02:00
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ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", _cerr, \
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2018-01-04 06:13:23 +01:00
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uc_strerror(_cerr)); \
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} \
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} while (0)
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static void InterruptHook(uc_engine* uc, u32 intNo, void* user_data) {
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u32 esr{};
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_ESR, &esr));
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auto ec = esr >> 26;
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auto iss = esr & 0xFFFFFF;
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switch (ec) {
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case 0x15: // SVC
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Kernel::CallSVC(iss);
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break;
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}
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}
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static bool UnmappedMemoryHook(uc_engine* uc, uc_mem_type type, u64 addr, int size, u64 value,
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void* user_data) {
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ARM_Interface::ThreadContext ctx{};
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Core::CPU().SaveContext(ctx);
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2018-04-27 13:54:05 +02:00
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ASSERT_MSG(false, "Attempted to read from unmapped memory: {:#X}, pc={:#X}, lr={:#X}", addr,
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2018-02-22 11:04:23 +01:00
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ctx.pc, ctx.cpu_registers[30]);
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2018-01-04 06:13:23 +01:00
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return {};
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}
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ARM_Unicorn::ARM_Unicorn() {
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CHECKED(uc_open(UC_ARCH_ARM64, UC_MODE_ARM, &uc));
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auto fpv = 3 << 20;
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_CPACR_EL1, &fpv));
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uc_hook hook{};
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CHECKED(uc_hook_add(uc, &hook, UC_HOOK_INTR, (void*)InterruptHook, this, 0, -1));
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CHECKED(uc_hook_add(uc, &hook, UC_HOOK_MEM_INVALID, (void*)UnmappedMemoryHook, this, 0, -1));
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}
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ARM_Unicorn::~ARM_Unicorn() {
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CHECKED(uc_close(uc));
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}
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void ARM_Unicorn::MapBackingMemory(VAddr address, size_t size, u8* memory,
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Kernel::VMAPermission perms) {
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CHECKED(uc_mem_map_ptr(uc, address, size, static_cast<u32>(perms), memory));
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}
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2018-03-16 23:22:14 +01:00
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void ARM_Unicorn::UnmapMemory(VAddr address, size_t size) {
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CHECKED(uc_mem_unmap(uc, address, size));
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}
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2018-01-04 06:13:23 +01:00
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void ARM_Unicorn::SetPC(u64 pc) {
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_PC, &pc));
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}
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u64 ARM_Unicorn::GetPC() const {
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u64 val{};
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_PC, &val));
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return val;
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}
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u64 ARM_Unicorn::GetReg(int regn) const {
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u64 val{};
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auto treg = UC_ARM64_REG_SP;
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if (regn <= 28) {
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treg = (uc_arm64_reg)(UC_ARM64_REG_X0 + regn);
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} else if (regn < 31) {
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treg = (uc_arm64_reg)(UC_ARM64_REG_X29 + regn - 29);
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}
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CHECKED(uc_reg_read(uc, treg, &val));
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return val;
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}
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void ARM_Unicorn::SetReg(int regn, u64 val) {
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auto treg = UC_ARM64_REG_SP;
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if (regn <= 28) {
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treg = (uc_arm64_reg)(UC_ARM64_REG_X0 + regn);
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} else if (regn < 31) {
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treg = (uc_arm64_reg)(UC_ARM64_REG_X29 + regn - 29);
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}
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CHECKED(uc_reg_write(uc, treg, &val));
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}
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2018-01-09 22:33:46 +01:00
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u128 ARM_Unicorn::GetExtReg(int /*index*/) const {
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2018-01-04 06:13:23 +01:00
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UNIMPLEMENTED();
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static constexpr u128 res{};
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return res;
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}
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2018-01-09 22:33:46 +01:00
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void ARM_Unicorn::SetExtReg(int /*index*/, u128 /*value*/) {
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2018-01-04 06:13:23 +01:00
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UNIMPLEMENTED();
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}
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u32 ARM_Unicorn::GetVFPReg(int /*index*/) const {
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UNIMPLEMENTED();
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return {};
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}
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void ARM_Unicorn::SetVFPReg(int /*index*/, u32 /*value*/) {
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UNIMPLEMENTED();
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}
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u32 ARM_Unicorn::GetCPSR() const {
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u64 nzcv{};
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_NZCV, &nzcv));
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return static_cast<u32>(nzcv);
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}
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void ARM_Unicorn::SetCPSR(u32 cpsr) {
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u64 nzcv = cpsr;
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_NZCV, &nzcv));
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}
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VAddr ARM_Unicorn::GetTlsAddress() const {
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u64 base{};
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_TPIDRRO_EL0, &base));
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return base;
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}
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void ARM_Unicorn::SetTlsAddress(VAddr base) {
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_TPIDRRO_EL0, &base));
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}
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2018-02-14 18:47:48 +01:00
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void ARM_Unicorn::Run() {
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ExecuteInstructions(std::max(CoreTiming::GetDowncount(), 0));
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}
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void ARM_Unicorn::Step() {
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ExecuteInstructions(1);
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}
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2018-01-04 06:13:23 +01:00
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MICROPROFILE_DEFINE(ARM_Jit, "ARM JIT", "ARM JIT", MP_RGB(255, 64, 64));
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void ARM_Unicorn::ExecuteInstructions(int num_instructions) {
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MICROPROFILE_SCOPE(ARM_Jit);
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CHECKED(uc_emu_start(uc, GetPC(), 1ULL << 63, 0, num_instructions));
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CoreTiming::AddTicks(num_instructions);
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}
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void ARM_Unicorn::SaveContext(ARM_Interface::ThreadContext& ctx) {
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int uregs[32];
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void* tregs[32];
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_SP, &ctx.sp));
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_PC, &ctx.pc));
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_NZCV, &ctx.cpsr));
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for (auto i = 0; i < 29; ++i) {
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uregs[i] = UC_ARM64_REG_X0 + i;
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tregs[i] = &ctx.cpu_registers[i];
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}
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2018-01-09 22:33:46 +01:00
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uregs[29] = UC_ARM64_REG_X29;
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tregs[29] = (void*)&ctx.cpu_registers[29];
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uregs[30] = UC_ARM64_REG_X30;
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tregs[30] = (void*)&ctx.cpu_registers[30];
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2018-01-04 06:13:23 +01:00
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2018-01-09 22:33:46 +01:00
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CHECKED(uc_reg_read_batch(uc, uregs, tregs, 31));
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2018-01-04 06:13:23 +01:00
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ctx.tls_address = GetTlsAddress();
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for (int i = 0; i < 32; ++i) {
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uregs[i] = UC_ARM64_REG_Q0 + i;
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tregs[i] = &ctx.fpu_registers[i];
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}
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CHECKED(uc_reg_read_batch(uc, uregs, tregs, 32));
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}
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void ARM_Unicorn::LoadContext(const ARM_Interface::ThreadContext& ctx) {
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int uregs[32];
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void* tregs[32];
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_SP, &ctx.sp));
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_PC, &ctx.pc));
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_NZCV, &ctx.cpsr));
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for (int i = 0; i < 29; ++i) {
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uregs[i] = UC_ARM64_REG_X0 + i;
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tregs[i] = (void*)&ctx.cpu_registers[i];
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}
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2018-01-09 22:33:46 +01:00
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uregs[29] = UC_ARM64_REG_X29;
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tregs[29] = (void*)&ctx.cpu_registers[29];
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uregs[30] = UC_ARM64_REG_X30;
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tregs[30] = (void*)&ctx.cpu_registers[30];
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2018-01-04 06:13:23 +01:00
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2018-01-09 22:33:46 +01:00
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CHECKED(uc_reg_write_batch(uc, uregs, tregs, 31));
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2018-01-04 06:13:23 +01:00
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SetTlsAddress(ctx.tls_address);
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for (auto i = 0; i < 32; ++i) {
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uregs[i] = UC_ARM64_REG_Q0 + i;
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tregs[i] = (void*)&ctx.fpu_registers[i];
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}
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CHECKED(uc_reg_write_batch(uc, uregs, tregs, 32));
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}
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void ARM_Unicorn::PrepareReschedule() {
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CHECKED(uc_emu_stop(uc));
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}
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void ARM_Unicorn::ClearInstructionCache() {}
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