forked from suyu/suyu
91 lines
2.8 KiB
C++
91 lines
2.8 KiB
C++
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/maxwell/opcode.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class StoreSize : u64 {
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U8,
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S8,
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U16,
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S16,
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B32,
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B64,
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B128,
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};
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// See Table 28 in https://docs.nvidia.com/cuda/parallel-thread-execution/index.html
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enum class StoreCache : u64 {
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WB, // Cache write-back all coherent levels
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CG, // Cache at global level
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CS, // Cache streaming, likely to be accessed once
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WT, // Cache write-through (to system memory)
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};
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} // Anonymous namespace
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void TranslatorVisitor::STG(u64 insn) {
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// STG stores registers into global memory.
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> data_reg;
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BitField<8, 8, IR::Reg> addr_reg;
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BitField<45, 1, u64> e;
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BitField<46, 2, StoreCache> cache;
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BitField<48, 3, StoreSize> size;
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} const stg{insn};
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const IR::U64 address{[&]() -> IR::U64 {
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if (stg.e == 0) {
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// STG without .E uses a 32-bit pointer, zero-extend it
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return ir.ConvertU(64, X(stg.addr_reg));
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}
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if (!IR::IsAligned(stg.addr_reg, 2)) {
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throw NotImplementedException("Unaligned address register");
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}
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// Pack two registers to build the 32-bit address
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return ir.PackUint2x32(ir.CompositeConstruct(X(stg.addr_reg), X(stg.addr_reg + 1)));
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}()};
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switch (stg.size) {
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case StoreSize::U8:
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ir.WriteGlobalU8(address, X(stg.data_reg));
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break;
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case StoreSize::S8:
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ir.WriteGlobalS8(address, X(stg.data_reg));
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break;
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case StoreSize::U16:
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ir.WriteGlobalU16(address, X(stg.data_reg));
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break;
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case StoreSize::S16:
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ir.WriteGlobalS16(address, X(stg.data_reg));
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break;
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case StoreSize::B32:
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ir.WriteGlobal32(address, X(stg.data_reg));
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break;
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case StoreSize::B64: {
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if (!IR::IsAligned(stg.data_reg, 2)) {
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throw NotImplementedException("Unaligned data registers");
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}
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const IR::Value vector{ir.CompositeConstruct(X(stg.data_reg), X(stg.data_reg + 1))};
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ir.WriteGlobal64(address, vector);
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break;
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}
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case StoreSize::B128:
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if (!IR::IsAligned(stg.data_reg, 4)) {
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throw NotImplementedException("Unaligned data registers");
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}
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const IR::Value vector{ir.CompositeConstruct(X(stg.data_reg), X(stg.data_reg + 1),
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X(stg.data_reg + 2), X(stg.data_reg + 3))};
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ir.WriteGlobal128(address, vector);
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break;
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}
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}
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} // namespace Shader::Maxwell
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