2018-06-22 01:36:01 +02:00
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// Copyright 2018 yuzu Emulator Project
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2018-03-19 22:45:22 +01:00
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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2018-06-22 01:36:01 +02:00
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#include <map>
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2018-03-19 22:45:22 +01:00
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#include <memory>
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2018-06-26 21:05:13 +02:00
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#include <vector>
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2018-06-26 22:14:14 +02:00
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#include <boost/icl/interval_map.hpp>
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2018-08-06 05:30:18 +02:00
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2018-03-19 22:45:22 +01:00
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#include "common/common_types.h"
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#include "common/math_util.h"
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2018-06-24 15:50:08 +02:00
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#include "video_core/engines/maxwell_3d.h"
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2018-03-19 22:45:22 +01:00
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#include "video_core/renderer_opengl/gl_resource_manager.h"
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2018-03-27 04:46:11 +02:00
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#include "video_core/textures/texture.h"
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2018-03-19 22:45:22 +01:00
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2018-06-22 01:36:01 +02:00
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class CachedSurface;
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using Surface = std::shared_ptr<CachedSurface>;
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using SurfaceSurfaceRect_Tuple = std::tuple<Surface, Surface, MathUtil::Rectangle<u32>>;
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using PageMap = boost::icl::interval_map<u64, int>;
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2018-03-19 22:45:22 +01:00
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struct SurfaceParams {
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enum class PixelFormat {
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2018-08-10 17:44:43 +02:00
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ABGR8U = 0,
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ABGR8S = 1,
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2018-08-15 05:11:27 +02:00
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B5G6R5U = 2,
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A2B10G10R10U = 3,
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A1B5G5R5U = 4,
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R8U = 5,
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2018-08-12 03:44:42 +02:00
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R8UI = 6,
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RGBA16F = 7,
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2018-08-13 06:34:20 +02:00
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RGBA16U = 8,
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RGBA16UI = 9,
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R11FG11FB10F = 10,
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RGBA32UI = 11,
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DXT1 = 12,
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DXT23 = 13,
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DXT45 = 14,
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DXN1 = 15, // This is also known as BC4
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DXN2UNORM = 16,
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DXN2SNORM = 17,
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BC7U = 18,
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ASTC_2D_4X4 = 19,
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2018-08-15 02:31:19 +02:00
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G8R8U = 20,
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G8R8S = 21,
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BGRA8 = 22,
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RGBA32F = 23,
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RG32F = 24,
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R32F = 25,
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R16F = 26,
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R16U = 27,
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R16S = 28,
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R16UI = 29,
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R16I = 30,
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RG16 = 31,
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RG16F = 32,
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RG16UI = 33,
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RG16I = 34,
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RG16S = 35,
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RGB32F = 36,
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SRGBA8 = 37,
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RG8U = 38,
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RG8S = 39,
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RG32UI = 40,
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R32UI = 41,
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2018-04-19 01:11:14 +02:00
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2018-07-02 19:42:04 +02:00
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MaxColorFormat,
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// DepthStencil formats
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Z24S8 = 42,
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S8Z24 = 43,
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Z32F = 44,
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Z16 = 45,
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Z32FS8 = 46,
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2018-07-02 19:42:04 +02:00
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MaxDepthStencilFormat,
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Max = MaxDepthStencilFormat,
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Invalid = 255,
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};
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2018-04-19 01:11:14 +02:00
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static constexpr size_t MaxPixelFormat = static_cast<size_t>(PixelFormat::Max);
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2018-04-18 21:17:05 +02:00
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enum class ComponentType {
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Invalid = 0,
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SNorm = 1,
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UNorm = 2,
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SInt = 3,
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UInt = 4,
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Float = 5,
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};
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2018-03-19 22:45:22 +01:00
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enum class SurfaceType {
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ColorTexture = 0,
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Depth = 1,
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DepthStencil = 2,
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Fill = 3,
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Invalid = 4,
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};
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2018-04-24 05:45:47 +02:00
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/**
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* Gets the compression factor for the specified PixelFormat. This applies to just the
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* "compressed width" and "compressed height", not the overall compression factor of a
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2018-06-22 01:36:01 +02:00
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* compressed image. This is used for maintaining proper surface sizes for compressed
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* texture formats.
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2018-04-24 05:45:47 +02:00
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*/
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2018-06-22 01:36:01 +02:00
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static constexpr u32 GetCompressionFactor(PixelFormat format) {
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2018-03-27 04:46:11 +02:00
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if (format == PixelFormat::Invalid)
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return 0;
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2018-04-24 05:45:47 +02:00
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constexpr std::array<u32, MaxPixelFormat> compression_factor_table = {{
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2018-08-10 17:44:43 +02:00
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1, // ABGR8U
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1, // ABGR8S
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2018-08-15 05:11:27 +02:00
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1, // B5G6R5U
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1, // A2B10G10R10U
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1, // A1B5G5R5U
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1, // R8U
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2018-08-12 03:44:42 +02:00
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1, // R8UI
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2018-06-06 04:55:17 +02:00
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1, // RGBA16F
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2018-08-13 06:34:20 +02:00
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1, // RGBA16U
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2018-08-13 06:04:52 +02:00
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1, // RGBA16UI
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2018-06-06 04:57:16 +02:00
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1, // R11FG11FB10F
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2018-06-30 21:23:13 +02:00
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1, // RGBA32UI
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2018-04-24 05:45:47 +02:00
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4, // DXT1
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4, // DXT23
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4, // DXT45
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2018-06-02 20:17:09 +02:00
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4, // DXN1
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2018-08-10 01:15:32 +02:00
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4, // DXN2UNORM
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4, // DXN2SNORM
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2018-07-05 00:22:48 +02:00
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4, // BC7U
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2018-06-26 21:05:13 +02:00
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4, // ASTC_2D_4X4
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2018-08-15 02:31:19 +02:00
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1, // G8R8U
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1, // G8R8S
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2018-07-23 22:56:52 +02:00
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1, // BGRA8
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2018-07-23 23:12:16 +02:00
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1, // RGBA32F
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2018-07-24 01:10:00 +02:00
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1, // RG32F
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2018-07-24 05:21:31 +02:00
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1, // R32F
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2018-07-24 20:39:16 +02:00
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1, // R16F
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2018-08-15 05:11:27 +02:00
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1, // R16U
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2018-08-11 20:01:50 +02:00
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1, // R16S
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1, // R16UI
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1, // R16I
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2018-07-26 02:01:29 +02:00
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1, // RG16
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1, // RG16F
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1, // RG16UI
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1, // RG16I
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1, // RG16S
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2018-08-02 20:56:38 +02:00
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1, // RGB32F
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2018-07-25 16:52:39 +02:00
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1, // SRGBA8
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2018-08-13 05:02:34 +02:00
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1, // RG8U
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2018-08-10 18:07:37 +02:00
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1, // RG8S
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2018-08-13 14:55:16 +02:00
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1, // RG32UI
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1, // R32UI
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2018-07-02 19:42:04 +02:00
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1, // Z24S8
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2018-07-03 20:05:13 +02:00
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1, // S8Z24
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2018-07-04 17:42:33 +02:00
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1, // Z32F
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2018-07-14 05:25:11 +02:00
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1, // Z16
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2018-07-25 03:41:40 +02:00
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1, // Z32FS8
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2018-04-24 05:45:47 +02:00
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}};
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ASSERT(static_cast<size_t>(format) < compression_factor_table.size());
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return compression_factor_table[static_cast<size_t>(format)];
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}
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static constexpr u32 GetFormatBpp(PixelFormat format) {
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if (format == PixelFormat::Invalid)
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return 0;
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constexpr std::array<u32, MaxPixelFormat> bpp_table = {{
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2018-08-10 17:44:43 +02:00
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32, // ABGR8U
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32, // ABGR8S
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2018-08-15 05:11:27 +02:00
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16, // B5G6R5U
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32, // A2B10G10R10U
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16, // A1B5G5R5U
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8, // R8U
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2018-08-12 03:44:42 +02:00
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8, // R8UI
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2018-05-31 04:24:07 +02:00
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64, // RGBA16F
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2018-08-13 06:34:20 +02:00
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64, // RGBA16U
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2018-08-13 06:04:52 +02:00
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64, // RGBA16UI
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2018-06-06 04:57:16 +02:00
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32, // R11FG11FB10F
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2018-06-30 21:23:13 +02:00
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128, // RGBA32UI
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2018-04-19 03:48:53 +02:00
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64, // DXT1
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128, // DXT23
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128, // DXT45
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2018-06-02 20:17:09 +02:00
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64, // DXN1
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2018-08-10 01:15:32 +02:00
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128, // DXN2UNORM
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128, // DXN2SNORM
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2018-07-05 00:22:48 +02:00
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128, // BC7U
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2018-06-18 05:50:44 +02:00
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32, // ASTC_2D_4X4
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2018-08-15 02:31:19 +02:00
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16, // G8R8U
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16, // G8R8S
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2018-07-23 22:56:52 +02:00
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32, // BGRA8
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2018-07-23 23:12:16 +02:00
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128, // RGBA32F
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2018-07-24 01:10:00 +02:00
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64, // RG32F
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2018-07-24 05:21:31 +02:00
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32, // R32F
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2018-07-24 20:39:16 +02:00
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16, // R16F
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2018-08-15 05:11:27 +02:00
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16, // R16U
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2018-08-11 20:01:50 +02:00
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16, // R16S
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16, // R16UI
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16, // R16I
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2018-07-26 02:01:29 +02:00
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32, // RG16
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32, // RG16F
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32, // RG16UI
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32, // RG16I
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32, // RG16S
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2018-08-02 20:56:38 +02:00
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96, // RGB32F
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2018-07-25 16:52:39 +02:00
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32, // SRGBA8
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2018-08-13 05:02:34 +02:00
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16, // RG8U
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2018-08-10 18:07:37 +02:00
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16, // RG8S
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2018-08-13 14:55:16 +02:00
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64, // RG32UI
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32, // R32UI
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2018-07-02 19:42:04 +02:00
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32, // Z24S8
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2018-07-03 20:05:13 +02:00
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32, // S8Z24
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2018-07-04 17:42:33 +02:00
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32, // Z32F
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2018-07-14 05:25:11 +02:00
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16, // Z16
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2018-07-25 03:41:40 +02:00
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64, // Z32FS8
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2018-04-24 05:45:47 +02:00
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}};
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2018-03-19 22:45:22 +01:00
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2018-03-27 04:46:11 +02:00
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ASSERT(static_cast<size_t>(format) < bpp_table.size());
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2018-03-19 22:45:22 +01:00
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return bpp_table[static_cast<size_t>(format)];
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}
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2018-07-21 20:36:32 +02:00
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2018-04-24 05:45:47 +02:00
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u32 GetFormatBpp() const {
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2018-03-19 22:45:22 +01:00
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return GetFormatBpp(pixel_format);
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}
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2018-07-02 19:42:04 +02:00
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static PixelFormat PixelFormatFromDepthFormat(Tegra::DepthFormat format) {
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switch (format) {
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2018-07-03 20:05:13 +02:00
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case Tegra::DepthFormat::S8_Z24_UNORM:
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return PixelFormat::S8Z24;
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2018-07-02 19:42:04 +02:00
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case Tegra::DepthFormat::Z24_S8_UNORM:
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return PixelFormat::Z24S8;
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2018-07-04 17:42:33 +02:00
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case Tegra::DepthFormat::Z32_FLOAT:
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return PixelFormat::Z32F;
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2018-07-14 05:25:11 +02:00
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case Tegra::DepthFormat::Z16_UNORM:
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return PixelFormat::Z16;
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2018-07-25 03:41:40 +02:00
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case Tegra::DepthFormat::Z32_S8_X24_FLOAT:
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return PixelFormat::Z32FS8;
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2018-07-02 19:42:04 +02:00
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default:
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2018-07-02 18:13:26 +02:00
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LOG_CRITICAL(HW_GPU, "Unimplemented format={}", static_cast<u32>(format));
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2018-07-02 19:42:04 +02:00
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UNREACHABLE();
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}
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}
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2018-03-24 05:47:33 +01:00
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static PixelFormat PixelFormatFromRenderTargetFormat(Tegra::RenderTargetFormat format) {
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switch (format) {
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2018-08-08 00:59:51 +02:00
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// TODO (Hexagon12): Converting SRGBA to RGBA is a hack and doesn't completely correct the
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// gamma.
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2018-05-27 16:02:05 +02:00
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case Tegra::RenderTargetFormat::RGBA8_SRGB:
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2018-07-25 16:52:39 +02:00
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case Tegra::RenderTargetFormat::RGBA8_UNORM:
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2018-08-10 17:44:43 +02:00
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return PixelFormat::ABGR8U;
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case Tegra::RenderTargetFormat::RGBA8_SNORM:
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return PixelFormat::ABGR8S;
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2018-07-23 22:56:52 +02:00
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case Tegra::RenderTargetFormat::BGRA8_UNORM:
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return PixelFormat::BGRA8;
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2018-04-23 17:50:28 +02:00
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case Tegra::RenderTargetFormat::RGB10_A2_UNORM:
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2018-08-15 05:11:27 +02:00
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return PixelFormat::A2B10G10R10U;
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2018-05-31 04:24:07 +02:00
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case Tegra::RenderTargetFormat::RGBA16_FLOAT:
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return PixelFormat::RGBA16F;
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2018-08-13 06:34:20 +02:00
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case Tegra::RenderTargetFormat::RGBA16_UNORM:
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return PixelFormat::RGBA16U;
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2018-08-13 06:04:52 +02:00
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case Tegra::RenderTargetFormat::RGBA16_UINT:
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return PixelFormat::RGBA16UI;
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2018-07-23 23:12:16 +02:00
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case Tegra::RenderTargetFormat::RGBA32_FLOAT:
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return PixelFormat::RGBA32F;
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2018-07-24 01:10:00 +02:00
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case Tegra::RenderTargetFormat::RG32_FLOAT:
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return PixelFormat::RG32F;
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2018-06-06 04:57:16 +02:00
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case Tegra::RenderTargetFormat::R11G11B10_FLOAT:
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return PixelFormat::R11FG11FB10F;
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2018-08-08 07:22:48 +02:00
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case Tegra::RenderTargetFormat::B5G6R5_UNORM:
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2018-08-15 05:11:27 +02:00
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return PixelFormat::B5G6R5U;
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2018-06-30 21:23:13 +02:00
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case Tegra::RenderTargetFormat::RGBA32_UINT:
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return PixelFormat::RGBA32UI;
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2018-07-24 23:47:50 +02:00
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case Tegra::RenderTargetFormat::R8_UNORM:
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2018-08-15 05:11:27 +02:00
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|
|
return PixelFormat::R8U;
|
2018-08-12 03:44:42 +02:00
|
|
|
case Tegra::RenderTargetFormat::R8_UINT:
|
|
|
|
return PixelFormat::R8UI;
|
2018-07-26 02:01:29 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG16_FLOAT:
|
|
|
|
return PixelFormat::RG16F;
|
|
|
|
case Tegra::RenderTargetFormat::RG16_UINT:
|
|
|
|
return PixelFormat::RG16UI;
|
|
|
|
case Tegra::RenderTargetFormat::RG16_SINT:
|
|
|
|
return PixelFormat::RG16I;
|
|
|
|
case Tegra::RenderTargetFormat::RG16_UNORM:
|
|
|
|
return PixelFormat::RG16;
|
|
|
|
case Tegra::RenderTargetFormat::RG16_SNORM:
|
|
|
|
return PixelFormat::RG16S;
|
2018-08-13 05:02:34 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG8_UNORM:
|
|
|
|
return PixelFormat::RG8U;
|
2018-08-10 18:07:37 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG8_SNORM:
|
|
|
|
return PixelFormat::RG8S;
|
2018-07-26 06:19:15 +02:00
|
|
|
case Tegra::RenderTargetFormat::R16_FLOAT:
|
|
|
|
return PixelFormat::R16F;
|
2018-08-11 20:01:50 +02:00
|
|
|
case Tegra::RenderTargetFormat::R16_UNORM:
|
2018-08-15 05:11:27 +02:00
|
|
|
return PixelFormat::R16U;
|
2018-08-11 20:01:50 +02:00
|
|
|
case Tegra::RenderTargetFormat::R16_SNORM:
|
|
|
|
return PixelFormat::R16S;
|
|
|
|
case Tegra::RenderTargetFormat::R16_UINT:
|
|
|
|
return PixelFormat::R16UI;
|
|
|
|
case Tegra::RenderTargetFormat::R16_SINT:
|
|
|
|
return PixelFormat::R16I;
|
2018-08-01 15:31:42 +02:00
|
|
|
case Tegra::RenderTargetFormat::R32_FLOAT:
|
|
|
|
return PixelFormat::R32F;
|
2018-08-13 14:55:16 +02:00
|
|
|
case Tegra::RenderTargetFormat::R32_UINT:
|
|
|
|
return PixelFormat::R32UI;
|
|
|
|
case Tegra::RenderTargetFormat::RG32_UINT:
|
|
|
|
return PixelFormat::RG32UI;
|
2018-03-24 05:47:33 +01:00
|
|
|
default:
|
2018-07-02 18:13:26 +02:00
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented format={}", static_cast<u32>(format));
|
2018-03-24 05:47:33 +01:00
|
|
|
UNREACHABLE();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-07-23 23:12:16 +02:00
|
|
|
static PixelFormat PixelFormatFromTextureFormat(Tegra::Texture::TextureFormat format,
|
|
|
|
Tegra::Texture::ComponentType component_type) {
|
2018-03-27 04:46:11 +02:00
|
|
|
// TODO(Subv): Properly implement this
|
|
|
|
switch (format) {
|
|
|
|
case Tegra::Texture::TextureFormat::A8R8G8B8:
|
2018-08-10 17:44:43 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
|
|
|
return PixelFormat::ABGR8U;
|
|
|
|
case Tegra::Texture::ComponentType::SNORM:
|
|
|
|
return PixelFormat::ABGR8S;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-04-19 01:11:14 +02:00
|
|
|
case Tegra::Texture::TextureFormat::B5G6R5:
|
2018-08-15 05:11:27 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
|
|
|
return PixelFormat::B5G6R5U;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-04-22 00:32:25 +02:00
|
|
|
case Tegra::Texture::TextureFormat::A2B10G10R10:
|
2018-08-15 05:11:27 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
|
|
|
return PixelFormat::A2B10G10R10U;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-05-27 16:02:05 +02:00
|
|
|
case Tegra::Texture::TextureFormat::A1B5G5R5:
|
2018-08-15 05:11:27 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
|
|
|
return PixelFormat::A1B5G5R5U;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-05-30 04:49:37 +02:00
|
|
|
case Tegra::Texture::TextureFormat::R8:
|
2018-08-12 03:44:42 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
2018-08-15 05:11:27 +02:00
|
|
|
return PixelFormat::R8U;
|
2018-08-12 03:44:42 +02:00
|
|
|
case Tegra::Texture::ComponentType::UINT:
|
|
|
|
return PixelFormat::R8UI;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-07-15 07:33:42 +02:00
|
|
|
case Tegra::Texture::TextureFormat::G8R8:
|
2018-08-15 02:31:19 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
|
|
|
return PixelFormat::G8R8U;
|
|
|
|
case Tegra::Texture::ComponentType::SNORM:
|
|
|
|
return PixelFormat::G8R8S;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-05-31 04:24:07 +02:00
|
|
|
case Tegra::Texture::TextureFormat::R16_G16_B16_A16:
|
2018-08-15 05:08:37 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
|
|
|
return PixelFormat::RGBA16U;
|
|
|
|
case Tegra::Texture::ComponentType::FLOAT:
|
|
|
|
return PixelFormat::RGBA16F;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-06-06 04:57:16 +02:00
|
|
|
case Tegra::Texture::TextureFormat::BF10GF11RF11:
|
2018-08-15 05:11:27 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::FLOAT:
|
|
|
|
return PixelFormat::R11FG11FB10F;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-06-30 21:23:13 +02:00
|
|
|
case Tegra::Texture::TextureFormat::R32_G32_B32_A32:
|
2018-07-23 23:12:16 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::FLOAT:
|
|
|
|
return PixelFormat::RGBA32F;
|
|
|
|
case Tegra::Texture::ComponentType::UINT:
|
|
|
|
return PixelFormat::RGBA32UI;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-07-24 01:10:00 +02:00
|
|
|
case Tegra::Texture::TextureFormat::R32_G32:
|
2018-08-13 14:55:16 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::FLOAT:
|
|
|
|
return PixelFormat::RG32F;
|
|
|
|
case Tegra::Texture::ComponentType::UINT:
|
|
|
|
return PixelFormat::RG32UI;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-08-02 20:56:38 +02:00
|
|
|
case Tegra::Texture::TextureFormat::R32_G32_B32:
|
2018-08-15 05:11:27 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::FLOAT:
|
|
|
|
return PixelFormat::RGB32F;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-07-24 20:39:16 +02:00
|
|
|
case Tegra::Texture::TextureFormat::R16:
|
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::FLOAT:
|
|
|
|
return PixelFormat::R16F;
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
2018-08-15 05:11:27 +02:00
|
|
|
return PixelFormat::R16U;
|
2018-08-11 20:01:50 +02:00
|
|
|
case Tegra::Texture::ComponentType::SNORM:
|
|
|
|
return PixelFormat::R16S;
|
|
|
|
case Tegra::Texture::ComponentType::UINT:
|
|
|
|
return PixelFormat::R16UI;
|
|
|
|
case Tegra::Texture::ComponentType::SINT:
|
|
|
|
return PixelFormat::R16I;
|
2018-07-24 20:39:16 +02:00
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-07-24 05:21:31 +02:00
|
|
|
case Tegra::Texture::TextureFormat::R32:
|
2018-08-13 14:55:16 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::FLOAT:
|
|
|
|
return PixelFormat::R32F;
|
|
|
|
case Tegra::Texture::ComponentType::UINT:
|
|
|
|
return PixelFormat::R32UI;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-07-25 00:14:59 +02:00
|
|
|
case Tegra::Texture::TextureFormat::ZF32:
|
|
|
|
return PixelFormat::Z32F;
|
2018-08-15 01:10:37 +02:00
|
|
|
case Tegra::Texture::TextureFormat::Z16:
|
|
|
|
return PixelFormat::Z16;
|
2018-07-24 23:45:16 +02:00
|
|
|
case Tegra::Texture::TextureFormat::Z24S8:
|
|
|
|
return PixelFormat::Z24S8;
|
2018-03-27 04:46:11 +02:00
|
|
|
case Tegra::Texture::TextureFormat::DXT1:
|
|
|
|
return PixelFormat::DXT1;
|
2018-04-19 03:48:53 +02:00
|
|
|
case Tegra::Texture::TextureFormat::DXT23:
|
|
|
|
return PixelFormat::DXT23;
|
|
|
|
case Tegra::Texture::TextureFormat::DXT45:
|
|
|
|
return PixelFormat::DXT45;
|
2018-06-02 20:17:09 +02:00
|
|
|
case Tegra::Texture::TextureFormat::DXN1:
|
|
|
|
return PixelFormat::DXN1;
|
2018-08-09 18:57:13 +02:00
|
|
|
case Tegra::Texture::TextureFormat::DXN2:
|
2018-08-10 01:15:32 +02:00
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
|
|
|
return PixelFormat::DXN2UNORM;
|
|
|
|
case Tegra::Texture::ComponentType::SNORM:
|
|
|
|
return PixelFormat::DXN2SNORM;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-07-05 00:22:48 +02:00
|
|
|
case Tegra::Texture::TextureFormat::BC7U:
|
|
|
|
return PixelFormat::BC7U;
|
2018-06-18 05:50:44 +02:00
|
|
|
case Tegra::Texture::TextureFormat::ASTC_2D_4X4:
|
|
|
|
return PixelFormat::ASTC_2D_4X4;
|
2018-07-26 02:01:29 +02:00
|
|
|
case Tegra::Texture::TextureFormat::R16_G16:
|
|
|
|
switch (component_type) {
|
|
|
|
case Tegra::Texture::ComponentType::FLOAT:
|
|
|
|
return PixelFormat::RG16F;
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
|
|
|
return PixelFormat::RG16;
|
|
|
|
case Tegra::Texture::ComponentType::SNORM:
|
|
|
|
return PixelFormat::RG16S;
|
|
|
|
case Tegra::Texture::ComponentType::UINT:
|
|
|
|
return PixelFormat::RG16UI;
|
|
|
|
case Tegra::Texture::ComponentType::SINT:
|
|
|
|
return PixelFormat::RG16I;
|
|
|
|
}
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component_type={}",
|
|
|
|
static_cast<u32>(component_type));
|
|
|
|
UNREACHABLE();
|
2018-03-27 04:46:11 +02:00
|
|
|
default:
|
2018-07-23 23:12:16 +02:00
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented format={}, component_type={}",
|
|
|
|
static_cast<u32>(format), static_cast<u32>(component_type));
|
2018-03-27 04:46:11 +02:00
|
|
|
UNREACHABLE();
|
|
|
|
}
|
2018-04-16 02:54:38 +02:00
|
|
|
}
|
|
|
|
|
2018-04-18 21:17:05 +02:00
|
|
|
static ComponentType ComponentTypeFromTexture(Tegra::Texture::ComponentType type) {
|
|
|
|
// TODO(Subv): Implement more component types
|
|
|
|
switch (type) {
|
|
|
|
case Tegra::Texture::ComponentType::UNORM:
|
|
|
|
return ComponentType::UNorm;
|
2018-07-23 23:12:16 +02:00
|
|
|
case Tegra::Texture::ComponentType::FLOAT:
|
|
|
|
return ComponentType::Float;
|
2018-07-26 02:01:29 +02:00
|
|
|
case Tegra::Texture::ComponentType::SNORM:
|
|
|
|
return ComponentType::SNorm;
|
|
|
|
case Tegra::Texture::ComponentType::UINT:
|
|
|
|
return ComponentType::UInt;
|
|
|
|
case Tegra::Texture::ComponentType::SINT:
|
|
|
|
return ComponentType::SInt;
|
2018-04-18 21:17:05 +02:00
|
|
|
default:
|
2018-07-02 18:13:26 +02:00
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented component type={}", static_cast<u32>(type));
|
2018-04-18 21:17:05 +02:00
|
|
|
UNREACHABLE();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static ComponentType ComponentTypeFromRenderTarget(Tegra::RenderTargetFormat format) {
|
|
|
|
// TODO(Subv): Implement more render targets
|
|
|
|
switch (format) {
|
|
|
|
case Tegra::RenderTargetFormat::RGBA8_UNORM:
|
2018-05-27 16:02:05 +02:00
|
|
|
case Tegra::RenderTargetFormat::RGBA8_SRGB:
|
2018-07-23 22:56:52 +02:00
|
|
|
case Tegra::RenderTargetFormat::BGRA8_UNORM:
|
2018-04-18 21:17:05 +02:00
|
|
|
case Tegra::RenderTargetFormat::RGB10_A2_UNORM:
|
2018-07-24 23:47:50 +02:00
|
|
|
case Tegra::RenderTargetFormat::R8_UNORM:
|
2018-07-26 02:01:29 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG16_UNORM:
|
2018-08-11 20:01:50 +02:00
|
|
|
case Tegra::RenderTargetFormat::R16_UNORM:
|
2018-08-08 07:22:48 +02:00
|
|
|
case Tegra::RenderTargetFormat::B5G6R5_UNORM:
|
2018-08-13 05:02:34 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG8_UNORM:
|
2018-08-13 06:34:20 +02:00
|
|
|
case Tegra::RenderTargetFormat::RGBA16_UNORM:
|
2018-04-18 21:17:05 +02:00
|
|
|
return ComponentType::UNorm;
|
2018-08-10 17:44:43 +02:00
|
|
|
case Tegra::RenderTargetFormat::RGBA8_SNORM:
|
2018-07-26 02:01:29 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG16_SNORM:
|
2018-08-11 20:01:50 +02:00
|
|
|
case Tegra::RenderTargetFormat::R16_SNORM:
|
2018-08-10 18:07:37 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG8_SNORM:
|
2018-07-26 02:01:29 +02:00
|
|
|
return ComponentType::SNorm;
|
2018-05-31 04:24:07 +02:00
|
|
|
case Tegra::RenderTargetFormat::RGBA16_FLOAT:
|
2018-06-06 04:57:16 +02:00
|
|
|
case Tegra::RenderTargetFormat::R11G11B10_FLOAT:
|
2018-07-23 23:12:16 +02:00
|
|
|
case Tegra::RenderTargetFormat::RGBA32_FLOAT:
|
2018-07-24 01:10:00 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG32_FLOAT:
|
2018-07-26 02:01:29 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG16_FLOAT:
|
2018-07-26 06:19:15 +02:00
|
|
|
case Tegra::RenderTargetFormat::R16_FLOAT:
|
2018-08-01 15:31:42 +02:00
|
|
|
case Tegra::RenderTargetFormat::R32_FLOAT:
|
2018-05-31 04:24:07 +02:00
|
|
|
return ComponentType::Float;
|
2018-06-30 21:23:13 +02:00
|
|
|
case Tegra::RenderTargetFormat::RGBA32_UINT:
|
2018-08-13 06:04:52 +02:00
|
|
|
case Tegra::RenderTargetFormat::RGBA16_UINT:
|
2018-07-26 02:01:29 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG16_UINT:
|
2018-08-12 03:44:42 +02:00
|
|
|
case Tegra::RenderTargetFormat::R8_UINT:
|
2018-08-11 20:01:50 +02:00
|
|
|
case Tegra::RenderTargetFormat::R16_UINT:
|
2018-08-13 14:55:16 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG32_UINT:
|
|
|
|
case Tegra::RenderTargetFormat::R32_UINT:
|
2018-06-30 21:23:13 +02:00
|
|
|
return ComponentType::UInt;
|
2018-07-26 02:01:29 +02:00
|
|
|
case Tegra::RenderTargetFormat::RG16_SINT:
|
2018-08-11 20:01:50 +02:00
|
|
|
case Tegra::RenderTargetFormat::R16_SINT:
|
2018-07-26 02:01:29 +02:00
|
|
|
return ComponentType::SInt;
|
2018-04-18 21:17:05 +02:00
|
|
|
default:
|
2018-07-02 18:13:26 +02:00
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented format={}", static_cast<u32>(format));
|
2018-04-18 21:17:05 +02:00
|
|
|
UNREACHABLE();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-24 23:42:29 +02:00
|
|
|
static PixelFormat PixelFormatFromGPUPixelFormat(Tegra::FramebufferConfig::PixelFormat format) {
|
|
|
|
switch (format) {
|
|
|
|
case Tegra::FramebufferConfig::PixelFormat::ABGR8:
|
2018-08-10 17:44:43 +02:00
|
|
|
return PixelFormat::ABGR8U;
|
2018-06-24 23:42:29 +02:00
|
|
|
default:
|
2018-07-02 18:13:26 +02:00
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented format={}", static_cast<u32>(format));
|
2018-06-24 23:42:29 +02:00
|
|
|
UNREACHABLE();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-07-02 19:42:04 +02:00
|
|
|
static ComponentType ComponentTypeFromDepthFormat(Tegra::DepthFormat format) {
|
|
|
|
switch (format) {
|
2018-07-14 05:25:11 +02:00
|
|
|
case Tegra::DepthFormat::Z16_UNORM:
|
2018-07-03 20:05:13 +02:00
|
|
|
case Tegra::DepthFormat::S8_Z24_UNORM:
|
2018-07-02 19:42:04 +02:00
|
|
|
case Tegra::DepthFormat::Z24_S8_UNORM:
|
|
|
|
return ComponentType::UNorm;
|
2018-07-04 17:42:33 +02:00
|
|
|
case Tegra::DepthFormat::Z32_FLOAT:
|
2018-07-25 03:41:40 +02:00
|
|
|
case Tegra::DepthFormat::Z32_S8_X24_FLOAT:
|
2018-07-04 17:42:33 +02:00
|
|
|
return ComponentType::Float;
|
2018-07-02 19:42:04 +02:00
|
|
|
default:
|
2018-07-02 18:13:26 +02:00
|
|
|
LOG_CRITICAL(HW_GPU, "Unimplemented format={}", static_cast<u32>(format));
|
2018-07-02 19:42:04 +02:00
|
|
|
UNREACHABLE();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-03-27 04:46:11 +02:00
|
|
|
static SurfaceType GetFormatType(PixelFormat pixel_format) {
|
2018-07-02 19:42:04 +02:00
|
|
|
if (static_cast<size_t>(pixel_format) < static_cast<size_t>(PixelFormat::MaxColorFormat)) {
|
2018-04-18 20:54:10 +02:00
|
|
|
return SurfaceType::ColorTexture;
|
2018-03-19 22:45:22 +01:00
|
|
|
}
|
|
|
|
|
2018-07-02 19:42:04 +02:00
|
|
|
if (static_cast<size_t>(pixel_format) <
|
|
|
|
static_cast<size_t>(PixelFormat::MaxDepthStencilFormat)) {
|
|
|
|
return SurfaceType::DepthStencil;
|
|
|
|
}
|
|
|
|
|
2018-03-27 04:46:11 +02:00
|
|
|
// TODO(Subv): Implement the other formats
|
|
|
|
ASSERT(false);
|
2018-03-19 22:45:22 +01:00
|
|
|
|
|
|
|
return SurfaceType::Invalid;
|
|
|
|
}
|
|
|
|
|
2018-06-26 22:14:14 +02:00
|
|
|
/// Returns the rectangle corresponding to this surface
|
2018-06-26 21:05:13 +02:00
|
|
|
MathUtil::Rectangle<u32> GetRect() const;
|
2018-03-19 22:45:22 +01:00
|
|
|
|
2018-06-26 22:14:14 +02:00
|
|
|
/// Returns the size of this surface in bytes, adjusted for compression
|
2018-06-22 01:36:01 +02:00
|
|
|
size_t SizeInBytes() const {
|
2018-06-24 15:50:08 +02:00
|
|
|
const u32 compression_factor{GetCompressionFactor(pixel_format)};
|
2018-06-22 01:36:01 +02:00
|
|
|
ASSERT(width % compression_factor == 0);
|
|
|
|
ASSERT(height % compression_factor == 0);
|
|
|
|
return (width / compression_factor) * (height / compression_factor) *
|
|
|
|
GetFormatBpp(pixel_format) / CHAR_BIT;
|
2018-03-19 22:45:22 +01:00
|
|
|
}
|
|
|
|
|
2018-06-26 22:14:14 +02:00
|
|
|
/// Returns the CPU virtual address for this surface
|
2018-04-24 06:19:36 +02:00
|
|
|
VAddr GetCpuAddr() const;
|
|
|
|
|
2018-06-26 22:14:14 +02:00
|
|
|
/// Returns true if the specified region overlaps with this surface's region in Switch memory
|
|
|
|
bool IsOverlappingRegion(Tegra::GPUVAddr region_addr, size_t region_size) const {
|
|
|
|
return addr <= (region_addr + region_size) && region_addr <= (addr + size_in_bytes);
|
|
|
|
}
|
|
|
|
|
2018-07-04 05:32:59 +02:00
|
|
|
/// Creates SurfaceParams from a texture configuration
|
2018-06-26 20:59:45 +02:00
|
|
|
static SurfaceParams CreateForTexture(const Tegra::Texture::FullTextureInfo& config);
|
|
|
|
|
2018-07-04 05:32:59 +02:00
|
|
|
/// Creates SurfaceParams from a framebuffer configuration
|
2018-06-26 20:59:45 +02:00
|
|
|
static SurfaceParams CreateForFramebuffer(
|
|
|
|
const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config);
|
|
|
|
|
2018-07-04 05:32:59 +02:00
|
|
|
/// Creates SurfaceParams for a depth buffer configuration
|
2018-07-21 20:29:36 +02:00
|
|
|
static SurfaceParams CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
|
|
|
|
Tegra::GPUVAddr zeta_address,
|
|
|
|
Tegra::DepthFormat format);
|
2018-07-04 05:32:59 +02:00
|
|
|
|
2018-07-21 20:36:32 +02:00
|
|
|
bool operator==(const SurfaceParams& other) const {
|
|
|
|
return std::tie(addr, is_tiled, block_height, pixel_format, component_type, type, width,
|
|
|
|
height, unaligned_height, size_in_bytes) ==
|
|
|
|
std::tie(other.addr, other.is_tiled, other.block_height, other.pixel_format,
|
|
|
|
other.component_type, other.type, other.width, other.height,
|
|
|
|
other.unaligned_height, other.size_in_bytes);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool operator!=(const SurfaceParams& other) const {
|
|
|
|
return !operator==(other);
|
|
|
|
}
|
|
|
|
|
2018-08-06 05:30:18 +02:00
|
|
|
/// Checks if surfaces are compatible for caching
|
|
|
|
bool IsCompatibleSurface(const SurfaceParams& other) const {
|
|
|
|
return std::tie(pixel_format, type, cache_width, cache_height) ==
|
|
|
|
std::tie(other.pixel_format, other.type, other.cache_width, other.cache_height);
|
|
|
|
}
|
|
|
|
|
2018-06-26 20:59:45 +02:00
|
|
|
Tegra::GPUVAddr addr;
|
|
|
|
bool is_tiled;
|
|
|
|
u32 block_height;
|
|
|
|
PixelFormat pixel_format;
|
|
|
|
ComponentType component_type;
|
|
|
|
SurfaceType type;
|
|
|
|
u32 width;
|
|
|
|
u32 height;
|
2018-06-26 21:05:13 +02:00
|
|
|
u32 unaligned_height;
|
2018-06-26 20:59:45 +02:00
|
|
|
size_t size_in_bytes;
|
2018-08-06 05:30:18 +02:00
|
|
|
|
|
|
|
// Parameters used for caching only
|
|
|
|
u32 cache_width;
|
|
|
|
u32 cache_height;
|
2018-06-26 20:59:45 +02:00
|
|
|
};
|
|
|
|
|
2018-06-22 01:36:01 +02:00
|
|
|
class CachedSurface final {
|
|
|
|
public:
|
|
|
|
CachedSurface(const SurfaceParams& params);
|
2018-03-19 22:45:22 +01:00
|
|
|
|
2018-06-22 01:36:01 +02:00
|
|
|
const OGLTexture& Texture() const {
|
|
|
|
return texture;
|
2018-03-19 22:45:22 +01:00
|
|
|
}
|
|
|
|
|
2018-06-22 01:36:01 +02:00
|
|
|
static constexpr unsigned int GetGLBytesPerPixel(SurfaceParams::PixelFormat format) {
|
|
|
|
if (format == SurfaceParams::PixelFormat::Invalid)
|
2018-03-27 04:46:11 +02:00
|
|
|
return 0;
|
|
|
|
|
2018-04-25 00:01:06 +02:00
|
|
|
return SurfaceParams::GetFormatBpp(format) / CHAR_BIT;
|
2018-03-19 22:45:22 +01:00
|
|
|
}
|
|
|
|
|
2018-06-22 01:36:01 +02:00
|
|
|
const SurfaceParams& GetSurfaceParams() const {
|
|
|
|
return params;
|
|
|
|
}
|
2018-03-19 22:45:22 +01:00
|
|
|
|
2018-03-23 04:06:54 +01:00
|
|
|
// Read/Write data in Switch memory to/from gl_buffer
|
2018-06-22 01:36:01 +02:00
|
|
|
void LoadGLBuffer();
|
|
|
|
void FlushGLBuffer();
|
2018-03-19 22:45:22 +01:00
|
|
|
|
|
|
|
// Upload/Download data in gl_buffer in/to this surface's texture
|
2018-06-22 01:36:01 +02:00
|
|
|
void UploadGLTexture(GLuint read_fb_handle, GLuint draw_fb_handle);
|
|
|
|
void DownloadGLTexture(GLuint read_fb_handle, GLuint draw_fb_handle);
|
|
|
|
|
|
|
|
private:
|
|
|
|
OGLTexture texture;
|
2018-06-26 21:05:13 +02:00
|
|
|
std::vector<u8> gl_buffer;
|
2018-06-22 01:36:01 +02:00
|
|
|
SurfaceParams params;
|
2018-03-19 22:45:22 +01:00
|
|
|
};
|
|
|
|
|
2018-06-22 01:36:01 +02:00
|
|
|
class RasterizerCacheOpenGL final : NonCopyable {
|
2018-03-19 22:45:22 +01:00
|
|
|
public:
|
|
|
|
RasterizerCacheOpenGL();
|
2018-06-26 22:14:14 +02:00
|
|
|
~RasterizerCacheOpenGL();
|
2018-03-19 22:45:22 +01:00
|
|
|
|
2018-06-26 22:14:14 +02:00
|
|
|
/// Get a surface based on the texture configuration
|
2018-03-27 04:46:11 +02:00
|
|
|
Surface GetTextureSurface(const Tegra::Texture::FullTextureInfo& config);
|
2018-06-26 22:14:14 +02:00
|
|
|
|
|
|
|
/// Get the color and depth surfaces based on the framebuffer configuration
|
2018-08-10 02:54:04 +02:00
|
|
|
SurfaceSurfaceRect_Tuple GetFramebufferSurfaces(bool using_color_fb, bool using_depth_fb);
|
2018-06-26 22:14:14 +02:00
|
|
|
|
2018-07-21 20:36:32 +02:00
|
|
|
/// Flushes the surface to Switch memory
|
|
|
|
void FlushSurface(const Surface& surface);
|
2018-06-26 22:14:14 +02:00
|
|
|
|
|
|
|
/// Tries to find a framebuffer GPU address based on the provided CPU address
|
2018-06-24 23:42:29 +02:00
|
|
|
Surface TryFindFramebufferSurface(VAddr cpu_addr) const;
|
2018-03-19 22:45:22 +01:00
|
|
|
|
2018-06-26 22:14:14 +02:00
|
|
|
/// Write any cached resources overlapping the region back to memory (if dirty)
|
|
|
|
void FlushRegion(Tegra::GPUVAddr addr, size_t size);
|
|
|
|
|
|
|
|
/// Mark the specified region as being invalidated
|
|
|
|
void InvalidateRegion(Tegra::GPUVAddr addr, size_t size);
|
|
|
|
|
2018-03-19 22:45:22 +01:00
|
|
|
private:
|
2018-06-26 22:14:14 +02:00
|
|
|
void LoadSurface(const Surface& surface);
|
2018-06-22 01:36:01 +02:00
|
|
|
Surface GetSurface(const SurfaceParams& params);
|
2018-03-19 22:45:22 +01:00
|
|
|
|
2018-07-21 22:04:01 +02:00
|
|
|
/// Recreates a surface with new parameters
|
|
|
|
Surface RecreateSurface(const Surface& surface, const SurfaceParams& new_params);
|
|
|
|
|
2018-06-26 22:14:14 +02:00
|
|
|
/// Register surface into the cache
|
|
|
|
void RegisterSurface(const Surface& surface);
|
|
|
|
|
|
|
|
/// Remove surface from the cache
|
|
|
|
void UnregisterSurface(const Surface& surface);
|
|
|
|
|
|
|
|
/// Increase/decrease the number of surface in pages touching the specified region
|
|
|
|
void UpdatePagesCachedCount(Tegra::GPUVAddr addr, u64 size, int delta);
|
|
|
|
|
2018-07-21 20:36:32 +02:00
|
|
|
std::unordered_map<Tegra::GPUVAddr, Surface> surface_cache;
|
2018-06-26 22:14:14 +02:00
|
|
|
PageMap cached_pages;
|
|
|
|
|
2018-03-19 22:45:22 +01:00
|
|
|
OGLFramebuffer read_framebuffer;
|
|
|
|
OGLFramebuffer draw_framebuffer;
|
|
|
|
};
|