2018-03-19 23:51:43 +01:00
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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2018-04-05 03:44:35 +02:00
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#include <map>
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#include <set>
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2018-03-19 23:51:43 +01:00
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#include <string>
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#include "common/assert.h"
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#include "common/common_types.h"
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2018-04-05 03:44:35 +02:00
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#include "video_core/engines/shader_bytecode.h"
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2018-03-19 23:51:43 +01:00
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#include "video_core/renderer_opengl/gl_shader_decompiler.h"
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2018-04-08 05:48:38 +02:00
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namespace GLShader {
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2018-03-19 23:51:43 +01:00
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namespace Decompiler {
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2018-04-08 05:48:38 +02:00
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using Tegra::Shader::Attribute;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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2018-04-10 07:26:15 +02:00
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using Tegra::Shader::Sampler;
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2018-04-10 05:39:44 +02:00
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using Tegra::Shader::SubOp;
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2018-04-08 05:48:38 +02:00
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using Tegra::Shader::Uniform;
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2018-03-19 23:51:43 +01:00
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constexpr u32 PROGRAM_END = MAX_PROGRAM_CODE_LENGTH;
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2018-04-05 03:44:35 +02:00
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class DecompileFail : public std::runtime_error {
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2018-03-19 23:51:43 +01:00
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public:
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2018-04-05 03:44:35 +02:00
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using std::runtime_error::runtime_error;
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};
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/// Describes the behaviour of code path of a given entry point and a return point.
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enum class ExitMethod {
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Undetermined, ///< Internal value. Only occur when analyzing JMP loop.
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AlwaysReturn, ///< All code paths reach the return point.
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Conditional, ///< Code path reaches the return point or an END instruction conditionally.
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AlwaysEnd, ///< All code paths reach a END instruction.
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};
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/// A subroutine is a range of code refereced by a CALL, IF or LOOP instruction.
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struct Subroutine {
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/// Generates a name suitable for GLSL source code.
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std::string GetName() const {
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return "sub_" + std::to_string(begin) + "_" + std::to_string(end);
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}
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u32 begin; ///< Entry point of the subroutine.
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u32 end; ///< Return point of the subroutine.
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ExitMethod exit_method; ///< Exit method of the subroutine.
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std::set<u32> labels; ///< Addresses refereced by JMP instructions.
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bool operator<(const Subroutine& rhs) const {
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return std::tie(begin, end) < std::tie(rhs.begin, rhs.end);
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}
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};
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/// Analyzes shader code and produces a set of subroutines.
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class ControlFlowAnalyzer {
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public:
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ControlFlowAnalyzer(const ProgramCode& program_code, u32 main_offset)
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: program_code(program_code) {
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// Recursively finds all subroutines.
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const Subroutine& program_main = AddSubroutine(main_offset, PROGRAM_END);
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if (program_main.exit_method != ExitMethod::AlwaysEnd)
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throw DecompileFail("Program does not always end");
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}
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std::set<Subroutine> GetSubroutines() {
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return std::move(subroutines);
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}
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private:
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const ProgramCode& program_code;
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std::set<Subroutine> subroutines;
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std::map<std::pair<u32, u32>, ExitMethod> exit_method_map;
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/// Adds and analyzes a new subroutine if it is not added yet.
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const Subroutine& AddSubroutine(u32 begin, u32 end) {
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auto iter = subroutines.find(Subroutine{begin, end});
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if (iter != subroutines.end())
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return *iter;
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Subroutine subroutine{begin, end};
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subroutine.exit_method = Scan(begin, end, subroutine.labels);
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if (subroutine.exit_method == ExitMethod::Undetermined)
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throw DecompileFail("Recursive function detected");
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return *subroutines.insert(std::move(subroutine)).first;
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}
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2018-04-05 03:44:35 +02:00
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/// Scans a range of code for labels and determines the exit method.
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ExitMethod Scan(u32 begin, u32 end, std::set<u32>& labels) {
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auto [iter, inserted] =
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exit_method_map.emplace(std::make_pair(begin, end), ExitMethod::Undetermined);
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ExitMethod& exit_method = iter->second;
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if (!inserted)
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return exit_method;
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for (u32 offset = begin; offset != end && offset != PROGRAM_END; ++offset) {
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const Instruction instr = {program_code[offset]};
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::EXIT: {
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return exit_method = ExitMethod::AlwaysEnd;
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}
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}
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}
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return exit_method = ExitMethod::AlwaysReturn;
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}
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};
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class ShaderWriter {
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public:
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void AddLine(const std::string& text) {
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DEBUG_ASSERT(scope >= 0);
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if (!text.empty()) {
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shader_source += std::string(static_cast<size_t>(scope) * 4, ' ');
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}
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shader_source += text + '\n';
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}
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std::string GetResult() {
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return std::move(shader_source);
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}
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int scope = 0;
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private:
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std::string shader_source;
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};
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class GLSLGenerator {
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public:
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GLSLGenerator(const std::set<Subroutine>& subroutines, const ProgramCode& program_code,
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2018-04-10 04:07:30 +02:00
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u32 main_offset, Maxwell3D::Regs::ShaderStage stage)
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: subroutines(subroutines), program_code(program_code), main_offset(main_offset),
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stage(stage) {
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2018-04-05 03:44:35 +02:00
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Generate();
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}
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std::string GetShaderCode() {
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return declarations.GetResult() + shader.GetResult();
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}
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2018-04-15 09:32:12 +02:00
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/// Returns entries in the shader that are useful for external functions
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ShaderEntries GetEntries() const {
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return {GetConstBuffersDeclarations()};
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}
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private:
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/// Gets the Subroutine object corresponding to the specified address.
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const Subroutine& GetSubroutine(u32 begin, u32 end) const {
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auto iter = subroutines.find(Subroutine{begin, end});
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ASSERT(iter != subroutines.end());
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return *iter;
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}
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/// Generates code representing an input attribute register.
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std::string GetInputAttribute(Attribute::Index attribute) {
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2018-04-16 02:26:45 +02:00
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switch (attribute) {
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case Attribute::Index::Position:
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return "position";
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default:
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const u32 index{static_cast<u32>(attribute) -
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static_cast<u32>(Attribute::Index::Attribute_0)};
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if (attribute >= Attribute::Index::Attribute_0) {
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declr_input_attribute.insert(attribute);
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return "input_attribute_" + std::to_string(index);
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}
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2018-04-08 05:48:38 +02:00
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2018-04-17 22:28:47 +02:00
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NGLOG_CRITICAL(HW_GPU, "Unhandled input attribute: {}", index);
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UNREACHABLE();
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}
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}
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/// Generates code representing an output attribute register.
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std::string GetOutputAttribute(Attribute::Index attribute) {
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switch (attribute) {
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case Attribute::Index::Position:
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return "position";
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default:
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const u32 index{static_cast<u32>(attribute) -
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static_cast<u32>(Attribute::Index::Attribute_0)};
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if (attribute >= Attribute::Index::Attribute_0) {
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declr_output_attribute.insert(attribute);
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return "output_attribute_" + std::to_string(index);
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}
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2018-04-17 22:28:47 +02:00
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NGLOG_CRITICAL(HW_GPU, "Unhandled output attribute: {}", index);
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2018-04-08 05:48:38 +02:00
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UNREACHABLE();
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}
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}
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2018-04-16 02:45:56 +02:00
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/// Generates code representing an immediate value
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static std::string GetImmediate(const Instruction& instr) {
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return std::to_string(instr.alu.GetImm20());
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}
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2018-04-08 05:48:38 +02:00
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/// Generates code representing a temporary (GPR) register.
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2018-04-10 07:26:15 +02:00
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std::string GetRegister(const Register& reg, unsigned elem = 0) {
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment && reg < 4) {
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2018-04-10 06:04:49 +02:00
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// GPRs 0-3 are output color for the fragment shader
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2018-04-16 02:47:41 +02:00
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return std::string{"color."} + "rgba"[(reg + elem) & 3];
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2018-04-10 06:04:49 +02:00
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}
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2018-04-10 07:26:15 +02:00
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return *declr_register.insert("register_" + std::to_string(reg + elem)).first;
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2018-04-08 05:48:38 +02:00
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}
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/// Generates code representing a uniform (C buffer) register.
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2018-04-15 09:32:12 +02:00
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std::string GetUniform(const Uniform& reg) {
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2018-04-17 22:33:05 +02:00
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declr_const_buffers[reg.index].MarkAsUsed(static_cast<unsigned>(reg.index),
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static_cast<unsigned>(reg.offset), stage);
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2018-04-15 09:32:12 +02:00
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return 'c' + std::to_string(reg.index) + '[' + std::to_string(reg.offset) + ']';
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2018-04-08 05:48:38 +02:00
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}
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2018-04-10 07:26:15 +02:00
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/// Generates code representing a texture sampler.
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std::string GetSampler(const Sampler& sampler) const {
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// TODO(Subv): Support more than just texture sampler 0
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ASSERT_MSG(sampler.index == Sampler::Index::Sampler_0, "unsupported");
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const unsigned index{static_cast<unsigned>(sampler.index.Value()) -
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static_cast<unsigned>(Sampler::Index::Sampler_0)};
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return "tex[" + std::to_string(index) + "]";
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}
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2018-04-08 05:48:38 +02:00
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/**
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* Adds code that calls a subroutine.
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* @param subroutine the subroutine to call.
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*/
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void CallSubroutine(const Subroutine& subroutine) {
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if (subroutine.exit_method == ExitMethod::AlwaysEnd) {
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shader.AddLine(subroutine.GetName() + "();");
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shader.AddLine("return true;");
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} else if (subroutine.exit_method == ExitMethod::Conditional) {
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shader.AddLine("if (" + subroutine.GetName() + "()) { return true; }");
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} else {
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shader.AddLine(subroutine.GetName() + "();");
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}
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}
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/**
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* Writes code that does an assignment operation.
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* @param reg the destination register code.
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* @param value the code representing the value to assign.
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*/
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void SetDest(u64 elem, const std::string& reg, const std::string& value,
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u64 dest_num_components, u64 value_num_components, bool is_abs = false) {
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2018-04-08 05:48:38 +02:00
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std::string swizzle = ".";
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swizzle += "xyzw"[elem];
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std::string dest = reg + (dest_num_components != 1 ? swizzle : "");
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std::string src = "(" + value + ")" + (value_num_components != 1 ? swizzle : "");
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2018-04-16 02:59:37 +02:00
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src = is_abs ? "abs(" + src + ")" : src;
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2018-04-08 05:48:38 +02:00
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shader.AddLine(dest + " = " + src + ";");
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}
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/**
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* Compiles a single instruction from Tegra to GLSL.
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* @param offset the offset of the Tegra shader instruction.
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* @return the offset of the next instruction to execute. Usually it is the current offset
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* + 1. If the current instruction always terminates the program, returns PROGRAM_END.
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*/
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u32 CompileInstr(u32 offset) {
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const Instruction instr = {program_code[offset]};
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shader.AddLine("// " + std::to_string(offset) + ": " + OpCode::GetInfo(instr.opcode).name);
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switch (OpCode::GetInfo(instr.opcode).type) {
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case OpCode::Type::Arithmetic: {
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2018-04-10 05:39:44 +02:00
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std::string dest = GetRegister(instr.gpr0);
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std::string op_a = instr.alu.negate_a ? "-" : "";
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op_a += GetRegister(instr.gpr8);
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if (instr.alu.abs_a) {
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op_a = "abs(" + op_a + ")";
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}
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std::string op_b = instr.alu.negate_b ? "-" : "";
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2018-04-16 02:45:56 +02:00
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if (instr.is_b_imm) {
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op_b += GetImmediate(instr);
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2018-04-10 05:39:44 +02:00
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} else {
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2018-04-16 02:45:56 +02:00
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if (instr.is_b_gpr) {
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op_b += GetRegister(instr.gpr20);
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} else {
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op_b += GetUniform(instr.uniform);
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}
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2018-04-10 05:39:44 +02:00
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}
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2018-04-16 02:45:56 +02:00
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2018-04-10 05:39:44 +02:00
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if (instr.alu.abs_b) {
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op_b = "abs(" + op_b + ")";
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}
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2018-04-08 05:48:38 +02:00
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switch (instr.opcode.EffectiveOpCode()) {
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2018-04-10 05:39:44 +02:00
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case OpCode::Id::FMUL_C:
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2018-04-16 02:45:56 +02:00
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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SetDest(0, dest, op_a + " * " + op_b, 1, 1, instr.alu.abs_d);
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2018-04-10 05:39:44 +02:00
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break;
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}
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case OpCode::Id::FADD_C:
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2018-04-16 02:45:56 +02:00
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case OpCode::Id::FADD_R:
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case OpCode::Id::FADD_IMM: {
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SetDest(0, dest, op_a + " + " + op_b, 1, 1, instr.alu.abs_d);
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2018-04-08 05:48:38 +02:00
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break;
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}
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2018-04-10 06:02:12 +02:00
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case OpCode::Id::MUFU: {
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switch (instr.sub_op) {
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2018-04-16 02:59:37 +02:00
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case SubOp::Cos:
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SetDest(0, dest, "cos(" + op_a + ")", 1, 1, instr.alu.abs_d);
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break;
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case SubOp::Sin:
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SetDest(0, dest, "sin(" + op_a + ")", 1, 1, instr.alu.abs_d);
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break;
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|
|
case SubOp::Ex2:
|
|
|
|
SetDest(0, dest, "exp2(" + op_a + ")", 1, 1, instr.alu.abs_d);
|
|
|
|
break;
|
|
|
|
case SubOp::Lg2:
|
|
|
|
SetDest(0, dest, "log2(" + op_a + ")", 1, 1, instr.alu.abs_d);
|
|
|
|
break;
|
2018-04-10 06:02:12 +02:00
|
|
|
case SubOp::Rcp:
|
2018-04-16 02:59:37 +02:00
|
|
|
SetDest(0, dest, "1.0 / " + op_a, 1, 1, instr.alu.abs_d);
|
|
|
|
break;
|
|
|
|
case SubOp::Rsq:
|
|
|
|
SetDest(0, dest, "inversesqrt(" + op_a + ")", 1, 1, instr.alu.abs_d);
|
|
|
|
break;
|
|
|
|
case SubOp::Min:
|
|
|
|
SetDest(0, dest, "min(" + op_a + "," + op_b + ")", 1, 1, instr.alu.abs_d);
|
2018-04-10 06:02:12 +02:00
|
|
|
break;
|
|
|
|
default:
|
2018-04-17 22:28:47 +02:00
|
|
|
NGLOG_CRITICAL(HW_GPU, "Unhandled MUFU sub op: {}",
|
|
|
|
static_cast<unsigned>(instr.sub_op.Value()));
|
|
|
|
UNREACHABLE();
|
2018-04-10 06:02:12 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2018-04-10 05:39:44 +02:00
|
|
|
default: {
|
2018-04-17 22:28:47 +02:00
|
|
|
NGLOG_CRITICAL(HW_GPU, "Unhandled arithmetic instruction: {} ({}): {}",
|
|
|
|
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
|
|
|
OpCode::GetInfo(instr.opcode).name, instr.hex);
|
|
|
|
UNREACHABLE();
|
2018-04-08 05:48:38 +02:00
|
|
|
}
|
2018-04-10 05:39:44 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case OpCode::Type::Ffma: {
|
|
|
|
std::string dest = GetRegister(instr.gpr0);
|
|
|
|
std::string op_a = GetRegister(instr.gpr8);
|
|
|
|
std::string op_b = instr.ffma.negate_b ? "-" : "";
|
|
|
|
std::string op_c = instr.ffma.negate_c ? "-" : "";
|
|
|
|
|
|
|
|
switch (instr.opcode.EffectiveOpCode()) {
|
2018-04-08 05:48:38 +02:00
|
|
|
case OpCode::Id::FFMA_CR: {
|
2018-04-16 02:45:56 +02:00
|
|
|
op_b += GetUniform(instr.uniform);
|
|
|
|
op_c += GetRegister(instr.gpr39);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case OpCode::Id::FFMA_RR: {
|
|
|
|
op_b += GetRegister(instr.gpr20);
|
|
|
|
op_c += GetRegister(instr.gpr39);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case OpCode::Id::FFMA_RC: {
|
|
|
|
op_b += GetRegister(instr.gpr39);
|
|
|
|
op_c += GetUniform(instr.uniform);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case OpCode::Id::FFMA_IMM: {
|
|
|
|
op_b += GetImmediate(instr);
|
|
|
|
op_c += GetRegister(instr.gpr39);
|
2018-04-08 05:48:38 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: {
|
2018-04-17 22:28:47 +02:00
|
|
|
NGLOG_CRITICAL(HW_GPU, "Unhandled FFMA instruction: {} ({}): {}",
|
|
|
|
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
|
|
|
OpCode::GetInfo(instr.opcode).name, instr.hex);
|
|
|
|
UNREACHABLE();
|
2018-04-08 05:48:38 +02:00
|
|
|
}
|
|
|
|
}
|
2018-04-16 02:45:56 +02:00
|
|
|
|
|
|
|
SetDest(0, dest, op_a + " * " + op_b + " + " + op_c, 1, 1);
|
2018-04-08 05:48:38 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case OpCode::Type::Memory: {
|
2018-04-10 05:39:44 +02:00
|
|
|
std::string gpr0 = GetRegister(instr.gpr0);
|
|
|
|
const Attribute::Index attribute = instr.attribute.fmt20.index;
|
2018-04-08 05:48:38 +02:00
|
|
|
|
|
|
|
switch (instr.opcode.EffectiveOpCode()) {
|
|
|
|
case OpCode::Id::LD_A: {
|
2018-04-10 07:26:15 +02:00
|
|
|
ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
|
2018-04-10 05:39:44 +02:00
|
|
|
SetDest(instr.attribute.fmt20.element, gpr0, GetInputAttribute(attribute), 1, 4);
|
2018-04-08 05:48:38 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case OpCode::Id::ST_A: {
|
2018-04-10 07:26:15 +02:00
|
|
|
ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
|
2018-04-10 05:39:44 +02:00
|
|
|
SetDest(instr.attribute.fmt20.element, GetOutputAttribute(attribute), gpr0, 4, 1);
|
2018-04-08 05:48:38 +02:00
|
|
|
break;
|
|
|
|
}
|
2018-04-10 07:26:15 +02:00
|
|
|
case OpCode::Id::TEXS: {
|
|
|
|
ASSERT_MSG(instr.attribute.fmt20.size == 4, "untested");
|
|
|
|
const std::string op_a = GetRegister(instr.gpr8);
|
|
|
|
const std::string op_b = GetRegister(instr.gpr20);
|
|
|
|
const std::string sampler = GetSampler(instr.sampler);
|
2018-04-19 20:33:17 +02:00
|
|
|
const std::string coord = "vec2 coords = vec2(" + op_a + ", " + op_b + ");";
|
|
|
|
// Add an extra scope and declare the texture coords inside to prevent overwriting
|
|
|
|
// them in case they are used as outputs of the texs instruction.
|
|
|
|
shader.AddLine("{");
|
|
|
|
++shader.scope;
|
|
|
|
shader.AddLine(coord);
|
|
|
|
const std::string texture = "texture(" + sampler + ", coords)";
|
2018-04-10 07:26:15 +02:00
|
|
|
for (unsigned elem = 0; elem < instr.attribute.fmt20.size; ++elem) {
|
|
|
|
SetDest(elem, GetRegister(instr.gpr0, elem), texture, 1, 4);
|
|
|
|
}
|
2018-04-19 20:33:17 +02:00
|
|
|
--shader.scope;
|
|
|
|
shader.AddLine("}");
|
2018-04-10 07:26:15 +02:00
|
|
|
break;
|
|
|
|
}
|
2018-04-08 05:48:38 +02:00
|
|
|
default: {
|
2018-04-17 22:28:47 +02:00
|
|
|
NGLOG_CRITICAL(HW_GPU, "Unhandled memory instruction: {} ({}): {}",
|
|
|
|
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
|
|
|
OpCode::GetInfo(instr.opcode).name, instr.hex);
|
|
|
|
UNREACHABLE();
|
2018-04-08 05:48:38 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
default: {
|
|
|
|
switch (instr.opcode.EffectiveOpCode()) {
|
|
|
|
case OpCode::Id::EXIT: {
|
|
|
|
shader.AddLine("return true;");
|
|
|
|
offset = PROGRAM_END - 1;
|
|
|
|
break;
|
|
|
|
}
|
2018-04-11 03:37:49 +02:00
|
|
|
case OpCode::Id::IPA: {
|
|
|
|
const auto& attribute = instr.attribute.fmt28;
|
|
|
|
std::string dest = GetRegister(instr.gpr0);
|
|
|
|
SetDest(attribute.element, dest, GetInputAttribute(attribute.index), 1, 4);
|
|
|
|
break;
|
|
|
|
}
|
2018-04-08 05:48:38 +02:00
|
|
|
default: {
|
2018-04-17 22:28:47 +02:00
|
|
|
NGLOG_CRITICAL(HW_GPU, "Unhandled instruction: {} ({}): {}",
|
|
|
|
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
|
|
|
OpCode::GetInfo(instr.opcode).name, instr.hex);
|
|
|
|
UNREACHABLE();
|
2018-04-08 05:48:38 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return offset + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Compiles a range of instructions from Tegra to GLSL.
|
|
|
|
* @param begin the offset of the starting instruction.
|
|
|
|
* @param end the offset where the compilation should stop (exclusive).
|
|
|
|
* @return the offset of the next instruction to compile. PROGRAM_END if the program
|
|
|
|
* terminates.
|
|
|
|
*/
|
|
|
|
u32 CompileRange(u32 begin, u32 end) {
|
|
|
|
u32 program_counter;
|
|
|
|
for (program_counter = begin; program_counter < (begin > end ? PROGRAM_END : end);) {
|
|
|
|
program_counter = CompileInstr(program_counter);
|
|
|
|
}
|
|
|
|
return program_counter;
|
|
|
|
}
|
|
|
|
|
|
|
|
void Generate() {
|
|
|
|
// Add declarations for all subroutines
|
|
|
|
for (const auto& subroutine : subroutines) {
|
|
|
|
shader.AddLine("bool " + subroutine.GetName() + "();");
|
|
|
|
}
|
|
|
|
shader.AddLine("");
|
|
|
|
|
|
|
|
// Add the main entry point
|
|
|
|
shader.AddLine("bool exec_shader() {");
|
|
|
|
++shader.scope;
|
|
|
|
CallSubroutine(GetSubroutine(main_offset, PROGRAM_END));
|
|
|
|
--shader.scope;
|
|
|
|
shader.AddLine("}\n");
|
|
|
|
|
|
|
|
// Add definitions for all subroutines
|
|
|
|
for (const auto& subroutine : subroutines) {
|
|
|
|
std::set<u32> labels = subroutine.labels;
|
|
|
|
|
|
|
|
shader.AddLine("bool " + subroutine.GetName() + "() {");
|
|
|
|
++shader.scope;
|
|
|
|
|
|
|
|
if (labels.empty()) {
|
|
|
|
if (CompileRange(subroutine.begin, subroutine.end) != PROGRAM_END) {
|
|
|
|
shader.AddLine("return false;");
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
labels.insert(subroutine.begin);
|
|
|
|
shader.AddLine("uint jmp_to = " + std::to_string(subroutine.begin) + "u;");
|
|
|
|
shader.AddLine("while (true) {");
|
|
|
|
++shader.scope;
|
|
|
|
|
|
|
|
shader.AddLine("switch (jmp_to) {");
|
|
|
|
|
|
|
|
for (auto label : labels) {
|
|
|
|
shader.AddLine("case " + std::to_string(label) + "u: {");
|
|
|
|
++shader.scope;
|
|
|
|
|
|
|
|
auto next_it = labels.lower_bound(label + 1);
|
|
|
|
u32 next_label = next_it == labels.end() ? subroutine.end : *next_it;
|
|
|
|
|
|
|
|
u32 compile_end = CompileRange(label, next_label);
|
|
|
|
if (compile_end > next_label && compile_end != PROGRAM_END) {
|
|
|
|
// This happens only when there is a label inside a IF/LOOP block
|
|
|
|
shader.AddLine("{ jmp_to = " + std::to_string(compile_end) + "u; break; }");
|
|
|
|
labels.emplace(compile_end);
|
|
|
|
}
|
|
|
|
|
|
|
|
--shader.scope;
|
|
|
|
shader.AddLine("}");
|
|
|
|
}
|
|
|
|
|
|
|
|
shader.AddLine("default: return false;");
|
|
|
|
shader.AddLine("}");
|
|
|
|
|
|
|
|
--shader.scope;
|
|
|
|
shader.AddLine("}");
|
|
|
|
|
|
|
|
shader.AddLine("return false;");
|
|
|
|
}
|
|
|
|
|
|
|
|
--shader.scope;
|
|
|
|
shader.AddLine("}\n");
|
|
|
|
|
|
|
|
DEBUG_ASSERT(shader.scope == 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
GenerateDeclarations();
|
|
|
|
}
|
|
|
|
|
2018-04-15 09:32:12 +02:00
|
|
|
/// Returns a list of constant buffer declarations
|
|
|
|
std::vector<ConstBufferEntry> GetConstBuffersDeclarations() const {
|
|
|
|
std::vector<ConstBufferEntry> result;
|
|
|
|
std::copy_if(declr_const_buffers.begin(), declr_const_buffers.end(),
|
|
|
|
std::back_inserter(result), [](const auto& entry) { return entry.IsUsed(); });
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2018-04-08 05:48:38 +02:00
|
|
|
/// Add declarations for registers
|
|
|
|
void GenerateDeclarations() {
|
|
|
|
for (const auto& reg : declr_register) {
|
|
|
|
declarations.AddLine("float " + reg + " = 0.0;");
|
|
|
|
}
|
|
|
|
declarations.AddLine("");
|
|
|
|
|
|
|
|
for (const auto& index : declr_input_attribute) {
|
|
|
|
// TODO(bunnei): Use proper number of elements for these
|
2018-04-14 21:57:58 +02:00
|
|
|
declarations.AddLine("layout(location = " +
|
|
|
|
std::to_string(static_cast<u32>(index) -
|
|
|
|
static_cast<u32>(Attribute::Index::Attribute_0)) +
|
|
|
|
") in vec4 " + GetInputAttribute(index) + ";");
|
2018-04-08 05:48:38 +02:00
|
|
|
}
|
|
|
|
declarations.AddLine("");
|
|
|
|
|
|
|
|
for (const auto& index : declr_output_attribute) {
|
|
|
|
// TODO(bunnei): Use proper number of elements for these
|
2018-04-14 21:57:58 +02:00
|
|
|
declarations.AddLine("layout(location = " +
|
|
|
|
std::to_string(static_cast<u32>(index) -
|
|
|
|
static_cast<u32>(Attribute::Index::Attribute_0)) +
|
|
|
|
") out vec4 " + GetOutputAttribute(index) + ";");
|
2018-04-08 05:48:38 +02:00
|
|
|
}
|
|
|
|
declarations.AddLine("");
|
2018-04-15 09:32:12 +02:00
|
|
|
|
|
|
|
unsigned const_buffer_layout = 0;
|
|
|
|
for (const auto& entry : GetConstBuffersDeclarations()) {
|
2018-04-15 21:42:23 +02:00
|
|
|
declarations.AddLine("layout(std430) buffer " + entry.GetName());
|
2018-04-15 09:32:12 +02:00
|
|
|
declarations.AddLine("{");
|
|
|
|
declarations.AddLine(" float c" + std::to_string(entry.GetIndex()) + "[];");
|
|
|
|
declarations.AddLine("};");
|
|
|
|
declarations.AddLine("");
|
|
|
|
++const_buffer_layout;
|
|
|
|
}
|
2018-03-19 23:51:43 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
2018-04-05 03:44:35 +02:00
|
|
|
const std::set<Subroutine>& subroutines;
|
|
|
|
const ProgramCode& program_code;
|
|
|
|
const u32 main_offset;
|
2018-04-10 04:07:30 +02:00
|
|
|
Maxwell3D::Regs::ShaderStage stage;
|
2018-04-05 03:44:35 +02:00
|
|
|
|
|
|
|
ShaderWriter shader;
|
2018-04-08 05:48:38 +02:00
|
|
|
ShaderWriter declarations;
|
2018-04-05 03:44:35 +02:00
|
|
|
|
2018-04-08 05:48:38 +02:00
|
|
|
// Declarations
|
|
|
|
std::set<std::string> declr_register;
|
|
|
|
std::set<Attribute::Index> declr_input_attribute;
|
|
|
|
std::set<Attribute::Index> declr_output_attribute;
|
2018-04-15 09:32:12 +02:00
|
|
|
std::array<ConstBufferEntry, Maxwell3D::Regs::MaxConstBuffers> declr_const_buffers;
|
|
|
|
};
|
2018-04-08 05:48:38 +02:00
|
|
|
|
|
|
|
std::string GetCommonDeclarations() {
|
|
|
|
return "bool exec_shader();";
|
|
|
|
}
|
2018-03-19 23:51:43 +01:00
|
|
|
|
2018-04-15 09:32:12 +02:00
|
|
|
boost::optional<ProgramResult> DecompileProgram(const ProgramCode& program_code, u32 main_offset,
|
|
|
|
Maxwell3D::Regs::ShaderStage stage) {
|
2018-04-05 03:44:35 +02:00
|
|
|
try {
|
|
|
|
auto subroutines = ControlFlowAnalyzer(program_code, main_offset).GetSubroutines();
|
2018-04-10 04:07:30 +02:00
|
|
|
GLSLGenerator generator(subroutines, program_code, main_offset, stage);
|
2018-04-15 09:32:12 +02:00
|
|
|
return ProgramResult{generator.GetShaderCode(), generator.GetEntries()};
|
2018-04-05 03:44:35 +02:00
|
|
|
} catch (const DecompileFail& exception) {
|
2018-04-17 22:28:47 +02:00
|
|
|
NGLOG_ERROR(HW_GPU, "Shader decompilation failed: {}", exception.what());
|
2018-04-05 03:44:35 +02:00
|
|
|
}
|
|
|
|
return boost::none;
|
2018-03-19 23:51:43 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
} // namespace Decompiler
|
2018-04-08 05:48:38 +02:00
|
|
|
} // namespace GLShader
|