436 lines
17 KiB
C++
436 lines
17 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <span>
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#include <tuple>
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#include <type_traits>
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#include <utility>
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#include <vector>
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/program.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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template <class Func>
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struct FuncTraits {};
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template <class ReturnType_, class... Args>
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struct FuncTraits<ReturnType_ (*)(Args...)> {
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using ReturnType = ReturnType_;
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static constexpr size_t NUM_ARGS = sizeof...(Args);
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template <size_t I>
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using ArgType = std::tuple_element_t<I, std::tuple<Args...>>;
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};
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template <auto func, typename... Args>
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void SetDefinition(EmitContext& ctx, IR::Inst* inst, Args... args) {
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inst->SetDefinition<Id>(func(ctx, std::forward<Args>(args)...));
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}
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template <typename ArgType>
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ArgType Arg(EmitContext& ctx, const IR::Value& arg) {
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if constexpr (std::is_same_v<ArgType, Id>) {
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return ctx.Def(arg);
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} else if constexpr (std::is_same_v<ArgType, const IR::Value&>) {
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return arg;
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} else if constexpr (std::is_same_v<ArgType, u32>) {
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return arg.U32();
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} else if constexpr (std::is_same_v<ArgType, IR::Block*>) {
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return arg.Label();
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} else if constexpr (std::is_same_v<ArgType, IR::Attribute>) {
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return arg.Attribute();
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} else if constexpr (std::is_same_v<ArgType, IR::Patch>) {
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return arg.Patch();
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} else if constexpr (std::is_same_v<ArgType, IR::Reg>) {
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return arg.Reg();
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}
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}
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template <auto func, bool is_first_arg_inst, size_t... I>
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void Invoke(EmitContext& ctx, IR::Inst* inst, std::index_sequence<I...>) {
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using Traits = FuncTraits<decltype(func)>;
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if constexpr (std::is_same_v<typename Traits::ReturnType, Id>) {
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if constexpr (is_first_arg_inst) {
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SetDefinition<func>(
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ctx, inst, inst,
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Arg<typename Traits::template ArgType<I + 2>>(ctx, inst->Arg(I))...);
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} else {
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SetDefinition<func>(
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ctx, inst, Arg<typename Traits::template ArgType<I + 1>>(ctx, inst->Arg(I))...);
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}
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} else {
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if constexpr (is_first_arg_inst) {
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func(ctx, inst, Arg<typename Traits::template ArgType<I + 2>>(ctx, inst->Arg(I))...);
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} else {
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func(ctx, Arg<typename Traits::template ArgType<I + 1>>(ctx, inst->Arg(I))...);
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}
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}
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}
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template <auto func>
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void Invoke(EmitContext& ctx, IR::Inst* inst) {
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using Traits = FuncTraits<decltype(func)>;
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static_assert(Traits::NUM_ARGS >= 1, "Insufficient arguments");
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if constexpr (Traits::NUM_ARGS == 1) {
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Invoke<func, false>(ctx, inst, std::make_index_sequence<0>{});
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} else {
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using FirstArgType = typename Traits::template ArgType<1>;
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static constexpr bool is_first_arg_inst = std::is_same_v<FirstArgType, IR::Inst*>;
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using Indices = std::make_index_sequence<Traits::NUM_ARGS - (is_first_arg_inst ? 2 : 1)>;
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Invoke<func, is_first_arg_inst>(ctx, inst, Indices{});
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}
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}
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void EmitInst(EmitContext& ctx, IR::Inst* inst) {
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switch (inst->GetOpcode()) {
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#define OPCODE(name, result_type, ...) \
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case IR::Opcode::name: \
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return Invoke<&Emit##name>(ctx, inst);
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#include "shader_recompiler/frontend/ir/opcodes.inc"
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#undef OPCODE
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}
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throw LogicError("Invalid opcode {}", inst->GetOpcode());
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}
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Id TypeId(const EmitContext& ctx, IR::Type type) {
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switch (type) {
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case IR::Type::U1:
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return ctx.U1;
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case IR::Type::U32:
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return ctx.U32[1];
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default:
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throw NotImplementedException("Phi node type {}", type);
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}
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}
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Id DefineMain(EmitContext& ctx, IR::Program& program) {
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const Id void_function{ctx.TypeFunction(ctx.void_id)};
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const Id main{ctx.OpFunction(ctx.void_id, spv::FunctionControlMask::MaskNone, void_function)};
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for (IR::Block* const block : program.blocks) {
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ctx.AddLabel(block->Definition<Id>());
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for (IR::Inst& inst : block->Instructions()) {
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EmitInst(ctx, &inst);
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}
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}
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ctx.OpFunctionEnd();
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return main;
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}
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spv::ExecutionMode ExecutionMode(TessPrimitive primitive) {
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switch (primitive) {
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case TessPrimitive::Isolines:
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return spv::ExecutionMode::Isolines;
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case TessPrimitive::Triangles:
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return spv::ExecutionMode::Triangles;
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case TessPrimitive::Quads:
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return spv::ExecutionMode::Quads;
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}
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throw InvalidArgument("Tessellation primitive {}", primitive);
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}
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spv::ExecutionMode ExecutionMode(TessSpacing spacing) {
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switch (spacing) {
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case TessSpacing::Equal:
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return spv::ExecutionMode::SpacingEqual;
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case TessSpacing::FractionalOdd:
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return spv::ExecutionMode::SpacingFractionalOdd;
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case TessSpacing::FractionalEven:
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return spv::ExecutionMode::SpacingFractionalEven;
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}
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throw InvalidArgument("Tessellation spacing {}", spacing);
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}
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void DefineEntryPoint(const IR::Program& program, EmitContext& ctx, Id main) {
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const std::span interfaces(ctx.interfaces.data(), ctx.interfaces.size());
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spv::ExecutionModel execution_model{};
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switch (program.stage) {
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case Stage::Compute: {
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const std::array<u32, 3> workgroup_size{program.workgroup_size};
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execution_model = spv::ExecutionModel::GLCompute;
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ctx.AddExecutionMode(main, spv::ExecutionMode::LocalSize, workgroup_size[0],
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workgroup_size[1], workgroup_size[2]);
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break;
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}
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case Stage::VertexB:
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execution_model = spv::ExecutionModel::Vertex;
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break;
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case Stage::TessellationControl:
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execution_model = spv::ExecutionModel::TessellationControl;
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ctx.AddCapability(spv::Capability::Tessellation);
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputVertices, program.invocations);
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break;
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case Stage::TessellationEval:
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execution_model = spv::ExecutionModel::TessellationEvaluation;
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ctx.AddCapability(spv::Capability::Tessellation);
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ctx.AddExecutionMode(main, ExecutionMode(ctx.profile.tess_primitive));
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ctx.AddExecutionMode(main, ExecutionMode(ctx.profile.tess_spacing));
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ctx.AddExecutionMode(main, ctx.profile.tess_clockwise ? spv::ExecutionMode::VertexOrderCw
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: spv::ExecutionMode::VertexOrderCcw);
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break;
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case Stage::Geometry:
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execution_model = spv::ExecutionModel::Geometry;
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ctx.AddCapability(spv::Capability::Geometry);
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ctx.AddCapability(spv::Capability::GeometryStreams);
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switch (ctx.profile.input_topology) {
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case InputTopology::Points:
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ctx.AddExecutionMode(main, spv::ExecutionMode::InputPoints);
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break;
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case InputTopology::Lines:
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ctx.AddExecutionMode(main, spv::ExecutionMode::InputLines);
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break;
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case InputTopology::LinesAdjacency:
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ctx.AddExecutionMode(main, spv::ExecutionMode::InputLinesAdjacency);
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break;
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case InputTopology::Triangles:
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ctx.AddExecutionMode(main, spv::ExecutionMode::Triangles);
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break;
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case InputTopology::TrianglesAdjacency:
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ctx.AddExecutionMode(main, spv::ExecutionMode::InputTrianglesAdjacency);
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break;
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}
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switch (program.output_topology) {
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case OutputTopology::PointList:
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputPoints);
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break;
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case OutputTopology::LineStrip:
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputLineStrip);
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break;
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case OutputTopology::TriangleStrip:
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputTriangleStrip);
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break;
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}
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if (program.info.stores_point_size) {
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ctx.AddCapability(spv::Capability::GeometryPointSize);
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}
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ctx.AddExecutionMode(main, spv::ExecutionMode::OutputVertices, program.output_vertices);
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ctx.AddExecutionMode(main, spv::ExecutionMode::Invocations, program.invocations);
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break;
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case Stage::Fragment:
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execution_model = spv::ExecutionModel::Fragment;
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if (ctx.profile.lower_left_origin_mode) {
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ctx.AddExecutionMode(main, spv::ExecutionMode::OriginLowerLeft);
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} else {
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ctx.AddExecutionMode(main, spv::ExecutionMode::OriginUpperLeft);
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}
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if (program.info.stores_frag_depth) {
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ctx.AddExecutionMode(main, spv::ExecutionMode::DepthReplacing);
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}
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if (ctx.profile.force_early_z) {
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ctx.AddExecutionMode(main, spv::ExecutionMode::EarlyFragmentTests);
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}
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break;
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default:
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throw NotImplementedException("Stage {}", program.stage);
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}
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ctx.AddEntryPoint(execution_model, main, "main", interfaces);
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}
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void SetupDenormControl(const Profile& profile, const IR::Program& program, EmitContext& ctx,
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Id main_func) {
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const Info& info{program.info};
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if (info.uses_fp32_denorms_flush && info.uses_fp32_denorms_preserve) {
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// LOG_ERROR(HW_GPU, "Fp32 denorm flush and preserve on the same shader");
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} else if (info.uses_fp32_denorms_flush) {
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if (profile.support_fp32_denorm_flush) {
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ctx.AddCapability(spv::Capability::DenormFlushToZero);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::DenormFlushToZero, 32U);
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} else {
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// Drivers will most likely flush denorms by default, no need to warn
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}
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} else if (info.uses_fp32_denorms_preserve) {
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if (profile.support_fp32_denorm_preserve) {
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ctx.AddCapability(spv::Capability::DenormPreserve);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::DenormPreserve, 32U);
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} else {
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// LOG_WARNING(HW_GPU, "Fp32 denorm preserve used in shader without host support");
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}
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}
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if (!profile.support_separate_denorm_behavior) {
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// No separate denorm behavior
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return;
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}
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if (info.uses_fp16_denorms_flush && info.uses_fp16_denorms_preserve) {
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// LOG_ERROR(HW_GPU, "Fp16 denorm flush and preserve on the same shader");
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} else if (info.uses_fp16_denorms_flush) {
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if (profile.support_fp16_denorm_flush) {
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ctx.AddCapability(spv::Capability::DenormFlushToZero);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::DenormFlushToZero, 16U);
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} else {
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// Same as fp32, no need to warn as most drivers will flush by default
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}
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} else if (info.uses_fp16_denorms_preserve) {
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if (profile.support_fp16_denorm_preserve) {
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ctx.AddCapability(spv::Capability::DenormPreserve);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::DenormPreserve, 16U);
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} else {
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// LOG_WARNING(HW_GPU, "Fp16 denorm preserve used in shader without host support");
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}
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}
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}
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void SetupSignedNanCapabilities(const Profile& profile, const IR::Program& program,
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EmitContext& ctx, Id main_func) {
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if (program.info.uses_fp16 && profile.support_fp16_signed_zero_nan_preserve) {
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ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 16U);
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}
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if (profile.support_fp32_signed_zero_nan_preserve) {
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ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 32U);
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}
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if (program.info.uses_fp64 && profile.support_fp64_signed_zero_nan_preserve) {
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ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
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ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 64U);
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}
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}
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void SetupCapabilities(const Profile& profile, const Info& info, EmitContext& ctx) {
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if (info.uses_sampled_1d) {
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ctx.AddCapability(spv::Capability::Sampled1D);
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}
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if (info.uses_sparse_residency) {
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ctx.AddCapability(spv::Capability::SparseResidency);
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}
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if (info.uses_demote_to_helper_invocation && profile.support_demote_to_helper_invocation) {
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ctx.AddExtension("SPV_EXT_demote_to_helper_invocation");
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ctx.AddCapability(spv::Capability::DemoteToHelperInvocationEXT);
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}
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if (info.stores_viewport_index) {
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ctx.AddCapability(spv::Capability::MultiViewport);
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}
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if (info.stores_viewport_mask && profile.support_viewport_mask) {
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ctx.AddExtension("SPV_NV_viewport_array2");
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ctx.AddCapability(spv::Capability::ShaderViewportMaskNV);
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}
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if (info.stores_layer || info.stores_viewport_index) {
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if (profile.support_viewport_index_layer_non_geometry && ctx.stage != Stage::Geometry) {
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ctx.AddExtension("SPV_EXT_shader_viewport_index_layer");
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ctx.AddCapability(spv::Capability::ShaderViewportIndexLayerEXT);
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}
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}
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if (!profile.support_vertex_instance_id && (info.loads_instance_id || info.loads_vertex_id)) {
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ctx.AddExtension("SPV_KHR_shader_draw_parameters");
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ctx.AddCapability(spv::Capability::DrawParameters);
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}
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if ((info.uses_subgroup_vote || info.uses_subgroup_invocation_id) && profile.support_vote) {
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ctx.AddExtension("SPV_KHR_shader_ballot");
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ctx.AddCapability(spv::Capability::SubgroupBallotKHR);
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if (!profile.warp_size_potentially_larger_than_guest) {
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// vote ops are only used when not taking the long path
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ctx.AddExtension("SPV_KHR_subgroup_vote");
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ctx.AddCapability(spv::Capability::SubgroupVoteKHR);
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}
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}
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if (info.uses_int64_bit_atomics && profile.support_int64_atomics) {
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ctx.AddCapability(spv::Capability::Int64Atomics);
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}
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if (info.uses_typeless_image_reads && profile.support_typeless_image_loads) {
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ctx.AddCapability(spv::Capability::StorageImageReadWithoutFormat);
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}
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if (info.uses_typeless_image_writes) {
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ctx.AddCapability(spv::Capability::StorageImageWriteWithoutFormat);
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}
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if (info.uses_image_buffers) {
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ctx.AddCapability(spv::Capability::ImageBuffer);
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}
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if (info.uses_sample_id) {
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ctx.AddCapability(spv::Capability::SampleRateShading);
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}
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if (!ctx.profile.xfb_varyings.empty()) {
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ctx.AddCapability(spv::Capability::TransformFeedback);
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}
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if (info.uses_derivatives) {
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ctx.AddCapability(spv::Capability::DerivativeControl);
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}
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// TODO: Track this usage
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ctx.AddCapability(spv::Capability::ImageGatherExtended);
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ctx.AddCapability(spv::Capability::ImageQuery);
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ctx.AddCapability(spv::Capability::SampledBuffer);
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}
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void PatchPhiNodes(IR::Program& program, EmitContext& ctx) {
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auto inst{program.blocks.front()->begin()};
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size_t block_index{0};
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ctx.PatchDeferredPhi([&](size_t phi_arg) {
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if (phi_arg == 0) {
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++inst;
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if (inst == program.blocks[block_index]->end() ||
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inst->GetOpcode() != IR::Opcode::Phi) {
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do {
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++block_index;
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inst = program.blocks[block_index]->begin();
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} while (inst->GetOpcode() != IR::Opcode::Phi);
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}
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}
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return ctx.Def(inst->Arg(phi_arg));
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});
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}
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} // Anonymous namespace
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std::vector<u32> EmitSPIRV(const Profile& profile, IR::Program& program, Bindings& binding) {
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EmitContext ctx{profile, program, binding};
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const Id main{DefineMain(ctx, program)};
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DefineEntryPoint(program, ctx, main);
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if (profile.support_float_controls) {
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ctx.AddExtension("SPV_KHR_float_controls");
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SetupDenormControl(profile, program, ctx, main);
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SetupSignedNanCapabilities(profile, program, ctx, main);
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}
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SetupCapabilities(profile, program.info, ctx);
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PatchPhiNodes(program, ctx);
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return ctx.Assemble();
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}
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Id EmitPhi(EmitContext& ctx, IR::Inst* inst) {
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const size_t num_args{inst->NumArgs()};
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boost::container::small_vector<Id, 32> blocks;
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blocks.reserve(num_args);
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for (size_t index = 0; index < num_args; ++index) {
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blocks.push_back(inst->PhiBlock(index)->Definition<Id>());
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}
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// The type of a phi instruction is stored in its flags
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const Id result_type{TypeId(ctx, inst->Flags<IR::Type>())};
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return ctx.DeferredOpPhi(result_type, std::span(blocks.data(), blocks.size()));
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}
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void EmitVoid(EmitContext&) {}
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Id EmitIdentity(EmitContext& ctx, const IR::Value& value) {
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const Id id{ctx.Def(value)};
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if (!Sirit::ValidId(id)) {
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throw NotImplementedException("Forward identity declaration");
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}
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return id;
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}
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void EmitGetZeroFromOp(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitGetSignFromOp(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitGetCarryFromOp(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitGetOverflowFromOp(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitGetSparseFromOp(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitGetInBoundsFromOp(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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} // namespace Shader::Backend::SPIRV
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