110 lines
2.8 KiB
C++
110 lines
2.8 KiB
C++
// Copyright 2020 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <memory>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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struct SwsContext;
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namespace Tegra {
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class GPU;
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class Nvdec;
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struct PlaneOffsets {
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u32 luma_offset{};
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u32 chroma_u_offset{};
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u32 chroma_v_offset{};
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};
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struct VicRegisters {
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INSERT_PADDING_WORDS(64);
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u32 nop{};
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INSERT_PADDING_WORDS(15);
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u32 pm_trigger{};
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INSERT_PADDING_WORDS(47);
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u32 set_application_id{};
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u32 set_watchdog_timer{};
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INSERT_PADDING_WORDS(17);
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u32 context_save_area{};
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u32 context_switch{};
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INSERT_PADDING_WORDS(43);
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u32 execute{};
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INSERT_PADDING_WORDS(63);
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std::array<std::array<PlaneOffsets, 8>, 8> surfacex_slots{};
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u32 picture_index{};
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u32 control_params{};
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u32 config_struct_offset{};
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u32 filter_struct_offset{};
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u32 palette_offset{};
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u32 hist_offset{};
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u32 context_id{};
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u32 fce_ucode_size{};
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PlaneOffsets output_surface{};
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u32 fce_ucode_offset{};
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INSERT_PADDING_WORDS(4);
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std::array<u32, 8> slot_context_id{};
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INSERT_PADDING_WORDS(16);
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};
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static_assert(sizeof(VicRegisters) == 0x7A0, "VicRegisters is an invalid size");
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class Vic {
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public:
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enum class Method : u32 {
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Execute = 0xc0,
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SetControlParams = 0x1c1,
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SetConfigStructOffset = 0x1c2,
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SetOutputSurfaceLumaOffset = 0x1c8,
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SetOutputSurfaceChromaUOffset = 0x1c9,
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SetOutputSurfaceChromaVOffset = 0x1ca
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};
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explicit Vic(GPU& gpu, std::shared_ptr<Nvdec> nvdec_processor);
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~Vic();
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/// Write to the device state.
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void ProcessMethod(Method method, const std::vector<u32>& arguments);
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private:
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void Execute();
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void VicStateWrite(u32 offset, u32 arguments);
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VicRegisters vic_state{};
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enum class VideoPixelFormat : u64_le {
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RGBA8 = 0x1f,
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BGRA8 = 0x20,
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Yuv420 = 0x44,
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};
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union VicConfig {
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u64_le raw{};
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BitField<0, 7, u64_le> pixel_format;
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BitField<7, 2, u64_le> chroma_loc_horiz;
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BitField<9, 2, u64_le> chroma_loc_vert;
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BitField<11, 4, u64_le> block_linear_kind;
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BitField<15, 4, u64_le> block_linear_height_log2;
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BitField<19, 3, u64_le> reserved0;
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BitField<22, 10, u64_le> reserved1;
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BitField<32, 14, u64_le> surface_width_minus1;
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BitField<46, 14, u64_le> surface_height_minus1;
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};
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GPU& gpu;
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std::shared_ptr<Tegra::Nvdec> nvdec_processor;
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GPUVAddr config_struct_address{};
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GPUVAddr output_surface_luma_address{};
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GPUVAddr output_surface_chroma_u_address{};
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GPUVAddr output_surface_chroma_v_address{};
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SwsContext* scaler_ctx{};
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s32 scaler_width{};
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s32 scaler_height{};
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};
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} // namespace Tegra
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