112 lines
2.7 KiB
C++
112 lines
2.7 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/arm/interpreter/arm_interpreter.h"
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const static cpu_config_t arm11_cpu_info = {
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"armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE
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};
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ARM_Interpreter::ARM_Interpreter() {
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state = new ARMul_State;
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ARMul_EmulateInit();
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memset(state, 0, sizeof(ARMul_State));
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ARMul_NewState(state);
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state->abort_model = 0;
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state->cpu = (cpu_config_t*)&arm11_cpu_info;
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state->bigendSig = LOW;
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ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
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state->lateabtSig = LOW;
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// Reset the core to initial state
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ARMul_CoProInit(state);
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ARMul_Reset(state);
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state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
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state->Emulate = 3;
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state->pc = state->Reg[15] = 0x00000000;
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state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
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state->servaddr = 0xFFFF0000;
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}
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ARM_Interpreter::~ARM_Interpreter() {
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delete state;
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}
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void ARM_Interpreter::SetPC(u32 pc) {
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state->pc = state->Reg[15] = pc;
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}
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u32 ARM_Interpreter::GetPC() const {
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return state->pc;
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}
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u32 ARM_Interpreter::GetReg(int index) const {
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return state->Reg[index];
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}
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void ARM_Interpreter::SetReg(int index, u32 value) {
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state->Reg[index] = value;
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}
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u32 ARM_Interpreter::GetCPSR() const {
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return state->Cpsr;
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}
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void ARM_Interpreter::SetCPSR(u32 cpsr) {
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state->Cpsr = cpsr;
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}
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u64 ARM_Interpreter::GetTicks() const {
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return state->NumInstrs;
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}
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void ARM_Interpreter::AddTicks(u64 ticks) {
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state->NumInstrs += ticks;
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}
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void ARM_Interpreter::ExecuteInstructions(int num_instructions) {
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state->NumInstrsToExecute = num_instructions - 1;
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ARMul_Emulate32(state);
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}
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void ARM_Interpreter::SaveContext(ThreadContext& ctx) {
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memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
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memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
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ctx.sp = state->Reg[13];
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ctx.lr = state->Reg[14];
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ctx.pc = state->pc;
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ctx.cpsr = state->Cpsr;
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ctx.fpscr = state->VFP[1];
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ctx.fpexc = state->VFP[2];
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ctx.reg_15 = state->Reg[15];
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ctx.mode = state->NextInstr;
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}
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void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
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memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
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memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
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state->Reg[13] = ctx.sp;
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state->Reg[14] = ctx.lr;
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state->pc = ctx.pc;
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state->Cpsr = ctx.cpsr;
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state->VFP[1] = ctx.fpscr;
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state->VFP[2] = ctx.fpexc;
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state->Reg[15] = ctx.reg_15;
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state->NextInstr = ctx.mode;
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}
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void ARM_Interpreter::PrepareReschedule() {
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state->NumInstrsToExecute = 0;
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}
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