shader: Implement NDC [-1, 1], attribute types and default varying initialization
This commit is contained in:
parent
1d2db78398
commit
68a9505d8a
15 changed files with 186 additions and 43 deletions
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@ -14,6 +14,7 @@ add_library(shader_recompiler STATIC
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backend/spirv/emit_spirv_logical.cpp
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backend/spirv/emit_spirv_memory.cpp
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backend/spirv/emit_spirv_select.cpp
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backend/spirv/emit_spirv_special.cpp
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backend/spirv/emit_spirv_undefined.cpp
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backend/spirv/emit_spirv_vote.cpp
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environment.h
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@ -67,6 +67,18 @@ Id DefineInput(EmitContext& ctx, Id type, std::optional<spv::BuiltIn> builtin =
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Id DefineOutput(EmitContext& ctx, Id type, std::optional<spv::BuiltIn> builtin = std::nullopt) {
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return DefineVariable(ctx, type, builtin, spv::StorageClass::Output);
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}
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Id GetAttributeType(EmitContext& ctx, AttributeType type) {
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switch (type) {
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case AttributeType::Float:
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return ctx.F32[4];
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case AttributeType::SignedInt:
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return ctx.TypeVector(ctx.TypeInt(32, true), 4);
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case AttributeType::UnsignedInt:
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return ctx.U32[4];
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}
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throw InvalidArgument("Invalid attribute type {}", type);
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}
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} // Anonymous namespace
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void VectorTypes::Define(Sirit::Module& sirit_ctx, Id base_type, std::string_view name) {
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@ -82,11 +94,11 @@ void VectorTypes::Define(Sirit::Module& sirit_ctx, Id base_type, std::string_vie
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}
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EmitContext::EmitContext(const Profile& profile_, IR::Program& program, u32& binding)
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: Sirit::Module(0x00010000), profile{profile_} {
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: Sirit::Module(0x00010000), profile{profile_}, stage{program.stage} {
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AddCapability(spv::Capability::Shader);
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DefineCommonTypes(program.info);
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DefineCommonConstants();
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DefineInterfaces(program.info, program.stage);
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DefineInterfaces(program.info);
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DefineConstantBuffers(program.info, binding);
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DefineStorageBuffers(program.info, binding);
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DefineTextures(program.info, binding);
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@ -130,6 +142,9 @@ void EmitContext::DefineCommonTypes(const Info& info) {
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U32.Define(*this, TypeInt(32, false), "u32");
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input_f32 = Name(TypePointer(spv::StorageClass::Input, F32[1]), "input_f32");
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input_u32 = Name(TypePointer(spv::StorageClass::Input, U32[1]), "input_u32");
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input_s32 = Name(TypePointer(spv::StorageClass::Input, TypeInt(32, true)), "input_s32");
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output_f32 = Name(TypePointer(spv::StorageClass::Output, F32[1]), "output_f32");
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if (info.uses_int8) {
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@ -162,9 +177,9 @@ void EmitContext::DefineCommonConstants() {
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u32_zero_value = Constant(U32[1], 0U);
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}
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void EmitContext::DefineInterfaces(const Info& info, Stage stage) {
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DefineInputs(info, stage);
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DefineOutputs(info, stage);
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void EmitContext::DefineInterfaces(const Info& info) {
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DefineInputs(info);
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DefineOutputs(info);
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}
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void EmitContext::DefineConstantBuffers(const Info& info, u32& binding) {
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@ -252,7 +267,7 @@ void EmitContext::DefineLabels(IR::Program& program) {
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}
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}
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void EmitContext::DefineInputs(const Info& info, Stage stage) {
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void EmitContext::DefineInputs(const Info& info) {
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if (info.uses_workgroup_id) {
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workgroup_id = DefineInput(*this, U32[3], spv::BuiltIn::WorkgroupId);
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}
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@ -288,8 +303,8 @@ void EmitContext::DefineInputs(const Info& info, Stage stage) {
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if (!info.loads_generics[index]) {
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continue;
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}
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// FIXME: Declare size from input
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const Id id{DefineInput(*this, F32[4])};
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const Id type{GetAttributeType(*this, profile.generic_input_types[index])};
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const Id id{DefineInput(*this, type)};
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Decorate(id, spv::Decoration::Location, static_cast<u32>(index));
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Name(id, fmt::format("in_attr{}", index));
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input_generics[index] = id;
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@ -323,8 +338,8 @@ void EmitContext::DefineConstantBuffers(const Info& info, Id UniformDefinitions:
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}
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}
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void EmitContext::DefineOutputs(const Info& info, Stage stage) {
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if (info.stores_position) {
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void EmitContext::DefineOutputs(const Info& info) {
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if (info.stores_position || stage == Stage::VertexB) {
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output_position = DefineOutput(*this, F32[4], spv::BuiltIn::Position);
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}
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for (size_t i = 0; i < info.stores_generics.size(); ++i) {
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@ -52,6 +52,7 @@ public:
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[[nodiscard]] Id Def(const IR::Value& value);
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const Profile& profile;
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Stage stage{};
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Id void_id{};
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Id U1{};
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@ -72,6 +73,9 @@ public:
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UniformDefinitions uniform_types;
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Id input_f32{};
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Id input_u32{};
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Id input_s32{};
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Id output_f32{};
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Id storage_u32{};
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@ -104,7 +108,7 @@ public:
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private:
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void DefineCommonTypes(const Info& info);
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void DefineCommonConstants();
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void DefineInterfaces(const Info& info, Stage stage);
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void DefineInterfaces(const Info& info);
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void DefineConstantBuffers(const Info& info, u32& binding);
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void DefineStorageBuffers(const Info& info, u32& binding);
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void DefineTextures(const Info& info, u32& binding);
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@ -113,8 +117,8 @@ private:
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void DefineConstantBuffers(const Info& info, Id UniformDefinitions::*member_type, u32 binding,
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Id type, char type_char, u32 element_size);
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void DefineInputs(const Info& info, Stage stage);
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void DefineOutputs(const Info& info, Stage stage);
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void DefineInputs(const Info& info);
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void DefineOutputs(const Info& info);
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};
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} // namespace Shader::Backend::SPIRV
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@ -28,6 +28,8 @@ void EmitLoopMerge(EmitContext& ctx, Id merge_label, Id continue_label);
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void EmitSelectionMerge(EmitContext& ctx, Id merge_label);
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void EmitReturn(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx, Id continue_label);
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void EmitPrologue(EmitContext& ctx);
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void EmitEpilogue(EmitContext& ctx);
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void EmitGetRegister(EmitContext& ctx);
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void EmitSetRegister(EmitContext& ctx);
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void EmitGetPred(EmitContext& ctx);
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@ -2,30 +2,26 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <tuple>
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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#pragma optimize("", off)
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namespace Shader::Backend::SPIRV {
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namespace {
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Id InputAttrPointer(EmitContext& ctx, IR::Attribute attr) {
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const u32 element{static_cast<u32>(attr) % 4};
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const auto element_id{[&] { return ctx.Constant(ctx.U32[1], element); }};
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if (IR::IsGeneric(attr)) {
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const u32 index{IR::GenericAttributeIndex(attr)};
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return ctx.OpAccessChain(ctx.input_f32, ctx.input_generics.at(index), element_id());
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}
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switch (attr) {
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case IR::Attribute::PositionX:
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case IR::Attribute::PositionY:
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case IR::Attribute::PositionZ:
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case IR::Attribute::PositionW:
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return ctx.OpAccessChain(ctx.input_f32, ctx.input_position, element_id());
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case IR::Attribute::InstanceId:
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return ctx.OpLoad(ctx.U32[1], ctx.instance_id);
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case IR::Attribute::VertexId:
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return ctx.OpLoad(ctx.U32[1], ctx.vertex_id);
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default:
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throw NotImplementedException("Read attribute {}", attr);
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std::tuple<Id, Id, bool> AttrTypes(EmitContext& ctx, u32 index) {
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const bool is_first_reader{ctx.stage == Stage::VertexB};
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const AttributeType type{ctx.profile.generic_input_types.at(index)};
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switch (type) {
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case AttributeType::Float:
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return {ctx.input_f32, ctx.F32[1], false};
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case AttributeType::UnsignedInt:
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return {ctx.input_u32, ctx.U32[1], true};
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case AttributeType::SignedInt:
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return {ctx.input_s32, ctx.TypeInt(32, true), true};
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}
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throw InvalidArgument("Invalid attribute type {}", type);
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}
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Id OutputAttrPointer(EmitContext& ctx, IR::Attribute attr) {
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@ -129,20 +125,41 @@ Id EmitGetCbufU64(EmitContext& ctx, const IR::Value& binding, const IR::Value& o
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}
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr) {
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if (!ctx.profile.support_vertex_instance_id) {
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const u32 element{static_cast<u32>(attr) % 4};
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const auto element_id{[&] { return ctx.Constant(ctx.U32[1], element); }};
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if (IR::IsGeneric(attr)) {
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const u32 index{IR::GenericAttributeIndex(attr)};
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const auto [pointer_type, type, needs_cast]{AttrTypes(ctx, index)};
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const Id generic_id{ctx.input_generics.at(index)};
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const Id pointer{ctx.OpAccessChain(pointer_type, generic_id, element_id())};
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const Id value{ctx.OpLoad(type, pointer)};
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return needs_cast ? ctx.OpBitcast(ctx.F32[1], value) : value;
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}
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switch (attr) {
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case IR::Attribute::PositionX:
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case IR::Attribute::PositionY:
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case IR::Attribute::PositionZ:
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case IR::Attribute::PositionW:
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return ctx.OpLoad(ctx.F32[1],
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ctx.OpAccessChain(ctx.input_f32, ctx.input_position, element_id()));
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case IR::Attribute::InstanceId:
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if (ctx.profile.support_vertex_instance_id) {
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return ctx.OpLoad(ctx.U32[1], ctx.instance_id);
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} else {
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return ctx.OpISub(ctx.U32[1], ctx.OpLoad(ctx.U32[1], ctx.instance_index),
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ctx.OpLoad(ctx.U32[1], ctx.base_instance));
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}
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case IR::Attribute::VertexId:
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if (ctx.profile.support_vertex_instance_id) {
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return ctx.OpLoad(ctx.U32[1], ctx.vertex_id);
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} else {
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return ctx.OpISub(ctx.U32[1], ctx.OpLoad(ctx.U32[1], ctx.vertex_index),
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ctx.OpLoad(ctx.U32[1], ctx.base_vertex));
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}
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default:
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break;
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throw NotImplementedException("Read attribute {}", attr);
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}
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}
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return ctx.OpLoad(ctx.F32[1], InputAttrPointer(ctx, attr));
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}
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void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value) {
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ctx.OpStore(OutputAttrPointer(ctx, attr), value);
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35
src/shader_recompiler/backend/spirv/emit_spirv_special.cpp
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35
src/shader_recompiler/backend/spirv/emit_spirv_special.cpp
Normal file
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@ -0,0 +1,35 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV {
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void EmitPrologue(EmitContext& ctx) {
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if (ctx.stage == Stage::VertexB) {
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const Id zero{ctx.Constant(ctx.F32[1], 0.0f)};
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const Id one{ctx.Constant(ctx.F32[1], 1.0f)};
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const Id null_vector{ctx.ConstantComposite(ctx.F32[4], zero, zero, zero, zero)};
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ctx.OpStore(ctx.output_position, ctx.ConstantComposite(ctx.F32[4], zero, zero, zero, one));
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for (const Id generic_id : ctx.output_generics) {
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if (Sirit::ValidId(generic_id)) {
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ctx.OpStore(generic_id, null_vector);
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}
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}
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}
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}
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void EmitEpilogue(EmitContext& ctx) {
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if (ctx.profile.convert_depth_mode) {
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const Id type{ctx.F32[1]};
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const Id position{ctx.OpLoad(ctx.F32[4], ctx.output_position)};
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const Id z{ctx.OpCompositeExtract(type, position, 2u)};
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const Id w{ctx.OpCompositeExtract(type, position, 3u)};
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const Id screen_depth{ctx.OpFMul(type, ctx.OpFAdd(type, z, w), ctx.Constant(type, 0.5f))};
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const Id vector{ctx.OpCompositeInsert(ctx.F32[4], screen_depth, position, 2u)};
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ctx.OpStore(ctx.output_position, vector);
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}
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}
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} // namespace Shader::Backend::SPIRV
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@ -92,6 +92,14 @@ void IREmitter::DemoteToHelperInvocation(Block* continue_label) {
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Inst(Opcode::DemoteToHelperInvocation, continue_label);
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}
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void IREmitter::Prologue() {
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Inst(Opcode::Prologue);
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}
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void IREmitter::Epilogue() {
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Inst(Opcode::Epilogue);
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}
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U32 IREmitter::GetReg(IR::Reg reg) {
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return Inst<U32>(Opcode::GetRegister, reg);
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}
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@ -39,6 +39,9 @@ public:
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void Return();
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void DemoteToHelperInvocation(Block* continue_label);
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void Prologue();
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void Epilogue();
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[[nodiscard]] U32 GetReg(IR::Reg reg);
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void SetReg(IR::Reg reg, const U32& value);
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@ -56,6 +56,8 @@ bool Inst::MayHaveSideEffects() const noexcept {
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case Opcode::SelectionMerge:
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case Opcode::Return:
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case Opcode::DemoteToHelperInvocation:
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case Opcode::Prologue:
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case Opcode::Epilogue:
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case Opcode::SetAttribute:
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case Opcode::SetAttributeIndexed:
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case Opcode::SetFragColor:
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@ -15,6 +15,10 @@ OPCODE(SelectionMerge, Void, Labe
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OPCODE(Return, Void, )
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OPCODE(DemoteToHelperInvocation, Void, Label, )
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// Special operations
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OPCODE(Prologue, Void, )
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OPCODE(Epilogue, Void, )
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// Context getters/setters
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OPCODE(GetRegister, U32, Reg, )
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OPCODE(SetRegister, Void, Reg, U32, )
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@ -634,6 +634,9 @@ public:
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: stmt_pool{stmt_pool_}, inst_pool{inst_pool_}, block_pool{block_pool_}, env{env_},
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block_list{block_list_} {
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Visit(root_stmt, nullptr, nullptr);
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IR::IREmitter ir{*block_list.front()};
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ir.Prologue();
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}
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private:
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current_block = block_pool.Create(inst_pool);
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block_list.push_back(current_block);
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}
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IR::IREmitter{*current_block}.Return();
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IR::IREmitter ir{*current_block};
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ir.Epilogue();
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ir.Return();
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current_block = nullptr;
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break;
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}
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@ -4,8 +4,18 @@
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#pragma once
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#include <array>
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#include "common/common_types.h"
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namespace Shader {
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enum class AttributeType : u8 {
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Float,
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SignedInt,
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UnsignedInt,
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};
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struct Profile {
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bool unified_descriptor_binding{};
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bool support_vertex_instance_id{};
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@ -24,6 +34,9 @@ struct Profile {
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// FClamp is broken and OpFMax + OpFMin should be used instead
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bool has_broken_spirv_clamp{};
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std::array<AttributeType, 32> generic_input_types{};
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bool convert_depth_mode{};
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};
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} // namespace Shader
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@ -181,6 +181,9 @@ void GraphicsPipeline::Configure(bool is_indexed) {
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PushImageDescriptors(stage_infos[stage], samplers.data(), image_view_ids.data(),
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*texture_cache, *update_descriptor_queue, index);
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}
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if (!descriptor_set_layout) {
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return;
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}
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const VkDescriptorSet descriptor_set{descriptor_allocator.Commit()};
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update_descriptor_queue->Send(*descriptor_update_template, descriptor_set);
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@ -437,7 +437,7 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, Tegra::GPU& gpu_,
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buffer_cache{buffer_cache_}, texture_cache{texture_cache_} {
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const auto& float_control{device.FloatControlProperties()};
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const VkDriverIdKHR driver_id{device.GetDriverID()};
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profile = Shader::Profile{
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base_profile = Shader::Profile{
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.unified_descriptor_binding = true,
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.support_vertex_instance_id = false,
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.support_float_controls = true,
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@ -458,6 +458,7 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, Tegra::GPU& gpu_,
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.support_vote = true,
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.warp_size_potentially_larger_than_guest = device.IsWarpSizePotentiallyBiggerThanGuest(),
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.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS_KHR,
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.generic_input_types{},
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};
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}
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@ -589,6 +590,7 @@ GraphicsPipeline PipelineCache::CreateGraphicsPipeline(ShaderPools& pools,
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Shader::Environment& env{*envs[env_index]};
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++env_index;
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const Shader::Profile profile{MakeProfile(key, env.ShaderStage())};
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const std::vector<u32> code{EmitSPIRV(profile, env, program, binding)};
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modules[stage_index] = BuildShader(device, code);
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}
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@ -645,9 +647,36 @@ ComputePipeline PipelineCache::CreateComputePipeline(ShaderPools& pools,
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Shader::Maxwell::Flow::CFG cfg{env, pools.flow_block, env.StartAddress()};
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Shader::IR::Program program{TranslateProgram(pools.inst, pools.block, env, cfg)};
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u32 binding{0};
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std::vector<u32> code{EmitSPIRV(profile, env, program, binding)};
|
||||
std::vector<u32> code{EmitSPIRV(base_profile, env, program, binding)};
|
||||
return ComputePipeline{device, descriptor_pool, update_descriptor_queue, program.info,
|
||||
BuildShader(device, code)};
|
||||
}
|
||||
|
||||
static Shader::AttributeType CastAttributeType(const FixedPipelineState::VertexAttribute& attr) {
|
||||
switch (attr.Type()) {
|
||||
case Maxwell::VertexAttribute::Type::SignedNorm:
|
||||
case Maxwell::VertexAttribute::Type::UnsignedNorm:
|
||||
case Maxwell::VertexAttribute::Type::UnsignedScaled:
|
||||
case Maxwell::VertexAttribute::Type::SignedScaled:
|
||||
case Maxwell::VertexAttribute::Type::Float:
|
||||
return Shader::AttributeType::Float;
|
||||
case Maxwell::VertexAttribute::Type::SignedInt:
|
||||
return Shader::AttributeType::SignedInt;
|
||||
case Maxwell::VertexAttribute::Type::UnsignedInt:
|
||||
return Shader::AttributeType::UnsignedInt;
|
||||
}
|
||||
return Shader::AttributeType::Float;
|
||||
}
|
||||
|
||||
Shader::Profile PipelineCache::MakeProfile(const GraphicsPipelineCacheKey& key,
|
||||
Shader::Stage stage) {
|
||||
Shader::Profile profile{base_profile};
|
||||
if (stage == Shader::Stage::VertexB) {
|
||||
profile.convert_depth_mode = key.state.ndc_minus_one_to_one != 0;
|
||||
std::ranges::transform(key.state.attributes, profile.generic_input_types.begin(),
|
||||
&CastAttributeType);
|
||||
}
|
||||
return profile;
|
||||
}
|
||||
|
||||
} // namespace Vulkan
|
||||
|
|
|
@ -156,6 +156,8 @@ private:
|
|||
ComputePipeline CreateComputePipeline(ShaderPools& pools, const ComputePipelineCacheKey& key,
|
||||
Shader::Environment& env) const;
|
||||
|
||||
Shader::Profile MakeProfile(const GraphicsPipelineCacheKey& key, Shader::Stage stage);
|
||||
|
||||
Tegra::GPU& gpu;
|
||||
Tegra::Engines::Maxwell3D& maxwell3d;
|
||||
Tegra::Engines::KeplerCompute& kepler_compute;
|
||||
|
@ -176,7 +178,7 @@ private:
|
|||
|
||||
ShaderPools main_pools;
|
||||
|
||||
Shader::Profile profile;
|
||||
Shader::Profile base_profile;
|
||||
std::string pipeline_cache_filename;
|
||||
};
|
||||
|
||||
|
|
Loading…
Reference in a new issue