3
0
Fork 0
forked from suyu/suyu

gl_shader_decompiler: Implement LOP32I LogicOperation PassB.

This commit is contained in:
bunnei 2018-06-15 19:41:23 -04:00
parent 17f3590d59
commit 61f9d9c4ab

View file

@ -930,20 +930,26 @@ private:
if (instr.alu.lop.invert_b)
imm = ~imm;
std::string op_b = std::to_string(imm);
switch (instr.alu.lop.operation) {
case Tegra::Shader::LogicOperation::And: {
regs.SetRegisterToInteger(instr.gpr0, true, 0,
'(' + op_a + " & " + std::to_string(imm) + ')', 1, 1);
regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " & " + op_b + ')',
1, 1);
break;
}
case Tegra::Shader::LogicOperation::Or: {
regs.SetRegisterToInteger(instr.gpr0, true, 0,
'(' + op_a + " | " + std::to_string(imm) + ')', 1, 1);
regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " | " + op_b + ')',
1, 1);
break;
}
case Tegra::Shader::LogicOperation::Xor: {
regs.SetRegisterToInteger(instr.gpr0, true, 0,
'(' + op_a + " ^ " + std::to_string(imm) + ')', 1, 1);
regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " ^ " + op_b + ')',
1, 1);
break;
}
case Tegra::Shader::LogicOperation::PassB: {
regs.SetRegisterToInteger(instr.gpr0, true, 0, op_b, 1, 1);
break;
}
default: