GPU: Implemented default vertex shader attributes.
Fixes some games crashing.
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Subv
parent
6f1143885b
commit
0e5ca080a8
4 changed files with 135 additions and 66 deletions
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@ -27,6 +27,10 @@ static int float_regs_counter = 0;
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static u32 uniform_write_buffer[4];
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static int default_attr_counter = 0;
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static u32 default_attr_write_buffer[3];
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Common::Profiling::TimingCategory category_drawing("Drawing");
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static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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@ -71,12 +75,9 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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u32 vertex_attribute_sources[16];
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boost::fill(vertex_attribute_sources, 0xdeadbeef);
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u32 vertex_attribute_strides[16];
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u32 vertex_attribute_formats[16];
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Regs::VertexAttributeFormat vertex_attribute_formats[16];
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// HACK: Initialize vertex_attribute_elements to zero to prevent infinite loops below.
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// This is one of the hacks required to deal with uninitalized vertex attributes.
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// TODO: Fix this properly.
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u32 vertex_attribute_elements[16] = {};
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u32 vertex_attribute_elements[16];
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u32 vertex_attribute_element_size[16];
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// Setup attribute data from loaders
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@ -90,7 +91,7 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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u32 attribute_index = loader_config.GetComponent(component);
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vertex_attribute_sources[attribute_index] = load_address;
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vertex_attribute_strides[attribute_index] = static_cast<u32>(loader_config.byte_count);
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vertex_attribute_formats[attribute_index] = static_cast<u32>(attribute_config.GetFormat(attribute_index));
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vertex_attribute_formats[attribute_index] = attribute_config.GetFormat(attribute_index);
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vertex_attribute_elements[attribute_index] = attribute_config.GetNumElements(attribute_index);
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vertex_attribute_element_size[attribute_index] = attribute_config.GetElementSizeInBytes(attribute_index);
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load_address += attribute_config.GetStride(attribute_index);
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@ -126,19 +127,21 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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input.attr[0].w = debug_token;
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for (int i = 0; i < attribute_config.GetNumTotalAttributes(); ++i) {
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if (attribute_config.IsDefaultAttribute(i)) {
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input.attr[i] = VertexShader::GetDefaultAttribute(i);
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LOG_TRACE(HW_GPU, "Loaded default attribute %x for vertex %x (index %x): (%f, %f, %f, %f)",
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i, vertex, index,
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input.attr[i][0].ToFloat32(), input.attr[i][1].ToFloat32(),
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input.attr[i][2].ToFloat32(), input.attr[i][3].ToFloat32());
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} else {
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for (unsigned int comp = 0; comp < vertex_attribute_elements[i]; ++comp) {
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const u8* srcdata = Memory::GetPointer(PAddrToVAddr(vertex_attribute_sources[i] + vertex_attribute_strides[i] * vertex + comp * vertex_attribute_element_size[i]));
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// TODO(neobrain): Ocarina of Time 3D has GetNumTotalAttributes return 8,
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// yet only provides 2 valid source data addresses. Need to figure out
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// what's wrong there, until then we just continue when address lookup fails
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if (srcdata == nullptr)
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continue;
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const float srcval = (vertex_attribute_formats[i] == 0) ? *(s8*)srcdata :
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(vertex_attribute_formats[i] == 1) ? *(u8*)srcdata :
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(vertex_attribute_formats[i] == 2) ? *(s16*)srcdata :
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const float srcval = (vertex_attribute_formats[i] == Regs::VertexAttributeFormat::BYTE) ? *(s8*)srcdata :
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(vertex_attribute_formats[i] == Regs::VertexAttributeFormat::UBYTE) ? *(u8*)srcdata :
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(vertex_attribute_formats[i] == Regs::VertexAttributeFormat::SHORT) ? *(s16*)srcdata :
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*(float*)srcdata;
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input.attr[i][comp] = float24::FromFloat32(srcval);
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LOG_TRACE(HW_GPU, "Loaded component %x of attribute %x for vertex %x (index %x) from 0x%08x + 0x%08lx + 0x%04lx: %f",
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comp, i, vertex, index,
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@ -148,6 +151,7 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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input.attr[i][comp].ToFloat32());
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}
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}
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}
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// HACK: Some games do not initialize the vertex position's w component. This leads
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// to critical issues since it messes up perspective division. As a
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@ -224,7 +228,7 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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// it directly write the values?
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uniform_write_buffer[float_regs_counter++] = value;
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// Uniforms are written in a packed format such that 4 float24 values are encoded in
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// Uniforms are written in a packed format such that four float24 values are encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if ((float_regs_counter >= 4 && uniform_setup.IsFloat32()) ||
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@ -260,6 +264,46 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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break;
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}
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// Load default vertex input attributes
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case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[0], 0x233):
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case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[1], 0x234):
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case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[2], 0x235):
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{
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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default_attr_write_buffer[default_attr_counter++] = value;
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// Default attributes are written in a packed format such that four float24 values are encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if (default_attr_counter >= 3) {
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default_attr_counter = 0;
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auto& setup = registers.vs_default_attributes_setup;
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if (setup.index >= 16) {
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LOG_ERROR(HW_GPU, "Invalid VS default attribute index %d", (int)setup.index);
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break;
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}
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Math::Vec4<float24>& attribute = VertexShader::GetDefaultAttribute(setup.index);
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// NOTE: The destination component order indeed is "backwards"
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attribute.w = float24::FromRawFloat24(default_attr_write_buffer[0] >> 8);
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attribute.z = float24::FromRawFloat24(((default_attr_write_buffer[0] & 0xFF) << 16) | ((default_attr_write_buffer[1] >> 16) & 0xFFFF));
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attribute.y = float24::FromRawFloat24(((default_attr_write_buffer[1] & 0xFFFF) << 8) | ((default_attr_write_buffer[2] >> 24) & 0xFF));
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attribute.x = float24::FromRawFloat24(default_attr_write_buffer[2] & 0xFFFFFF);
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LOG_TRACE(HW_GPU, "Set default VS attribute %x to (%f %f %f %f)", (int)setup.index,
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attribute.x.ToFloat32(), attribute.y.ToFloat32(), attribute.z.ToFloat32(),
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attribute.w.ToFloat32());
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// TODO: Verify that this actually modifies the register!
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setup.index = setup.index + 1;
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}
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break;
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}
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// Load shader program code
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[0], 0x2cc):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[1], 0x2cd):
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@ -489,14 +489,14 @@ struct Regs {
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INSERT_PADDING_WORDS(0xe0);
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struct {
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enum class Format : u64 {
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enum class VertexAttributeFormat : u64 {
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BYTE = 0,
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UBYTE = 1,
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SHORT = 2,
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FLOAT = 3,
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};
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struct {
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BitField<0, 29, u32> base_address;
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u32 GetPhysicalBaseAddress() const {
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@ -505,29 +505,29 @@ struct Regs {
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// Descriptor for internal vertex attributes
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union {
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BitField< 0, 2, Format> format0; // size of one element
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BitField< 0, 2, VertexAttributeFormat> format0; // size of one element
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BitField< 2, 2, u64> size0; // number of elements minus 1
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BitField< 4, 2, Format> format1;
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BitField< 4, 2, VertexAttributeFormat> format1;
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BitField< 6, 2, u64> size1;
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BitField< 8, 2, Format> format2;
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BitField< 8, 2, VertexAttributeFormat> format2;
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BitField<10, 2, u64> size2;
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BitField<12, 2, Format> format3;
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BitField<12, 2, VertexAttributeFormat> format3;
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BitField<14, 2, u64> size3;
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BitField<16, 2, Format> format4;
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BitField<16, 2, VertexAttributeFormat> format4;
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BitField<18, 2, u64> size4;
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BitField<20, 2, Format> format5;
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BitField<20, 2, VertexAttributeFormat> format5;
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BitField<22, 2, u64> size5;
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BitField<24, 2, Format> format6;
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BitField<24, 2, VertexAttributeFormat> format6;
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BitField<26, 2, u64> size6;
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BitField<28, 2, Format> format7;
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BitField<28, 2, VertexAttributeFormat> format7;
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BitField<30, 2, u64> size7;
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BitField<32, 2, Format> format8;
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BitField<32, 2, VertexAttributeFormat> format8;
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BitField<34, 2, u64> size8;
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BitField<36, 2, Format> format9;
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BitField<36, 2, VertexAttributeFormat> format9;
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BitField<38, 2, u64> size9;
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BitField<40, 2, Format> format10;
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BitField<40, 2, VertexAttributeFormat> format10;
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BitField<42, 2, u64> size10;
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BitField<44, 2, Format> format11;
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BitField<44, 2, VertexAttributeFormat> format11;
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BitField<46, 2, u64> size11;
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BitField<48, 12, u64> attribute_mask;
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@ -536,8 +536,8 @@ struct Regs {
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BitField<60, 4, u64> num_extra_attributes;
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};
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inline Format GetFormat(int n) const {
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Format formats[] = {
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inline VertexAttributeFormat GetFormat(int n) const {
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VertexAttributeFormat formats[] = {
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format0, format1, format2, format3,
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format4, format5, format6, format7,
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format8, format9, format10, format11
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@ -555,14 +555,18 @@ struct Regs {
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}
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inline int GetElementSizeInBytes(int n) const {
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return (GetFormat(n) == Format::FLOAT) ? 4 :
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(GetFormat(n) == Format::SHORT) ? 2 : 1;
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return (GetFormat(n) == VertexAttributeFormat::FLOAT) ? 4 :
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(GetFormat(n) == VertexAttributeFormat::SHORT) ? 2 : 1;
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}
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inline int GetStride(int n) const {
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return GetNumElements(n) * GetElementSizeInBytes(n);
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}
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inline bool IsDefaultAttribute(int id) const {
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return (id >= 12) || (attribute_mask & (1 << id)) != 0;
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}
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inline int GetNumTotalAttributes() const {
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return (int)num_extra_attributes+1;
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}
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@ -625,7 +629,18 @@ struct Regs {
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u32 trigger_draw;
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u32 trigger_draw_indexed;
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INSERT_PADDING_WORDS(0x2e);
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INSERT_PADDING_WORDS(0x2);
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// These registers are used to setup the default "fall-back" vertex shader attributes
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struct {
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// Index of the current default attribute
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u32 index;
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// Writing to these registers sets the "current" default attribute.
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u32 set_value[3];
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} vs_default_attributes_setup;
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INSERT_PADDING_WORDS(0x28);
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enum class TriangleTopology : u32 {
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List = 0,
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@ -669,7 +684,7 @@ struct Regs {
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BitField<56, 4, u64> attribute14_register;
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BitField<60, 4, u64> attribute15_register;
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int GetRegisterForAttribute(int attribute_index) {
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int GetRegisterForAttribute(int attribute_index) const {
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u64 fields[] = {
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attribute0_register, attribute1_register, attribute2_register, attribute3_register,
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attribute4_register, attribute5_register, attribute6_register, attribute7_register,
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@ -775,6 +790,7 @@ struct Regs {
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ADD_FIELD(num_vertices);
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ADD_FIELD(trigger_draw);
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ADD_FIELD(trigger_draw_indexed);
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ADD_FIELD(vs_default_attributes_setup);
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ADD_FIELD(triangle_topology);
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ADD_FIELD(vs_bool_uniforms);
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ADD_FIELD(vs_int_uniforms);
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@ -849,6 +865,7 @@ ASSERT_REG_POSITION(index_array, 0x227);
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ASSERT_REG_POSITION(num_vertices, 0x228);
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ASSERT_REG_POSITION(trigger_draw, 0x22e);
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ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(vs_default_attributes_setup, 0x232);
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ASSERT_REG_POSITION(triangle_topology, 0x25e);
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ASSERT_REG_POSITION(vs_bool_uniforms, 0x2b0);
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ASSERT_REG_POSITION(vs_int_uniforms, 0x2b1);
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@ -35,6 +35,8 @@ static struct {
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std::array<Math::Vec4<u8>,4> i;
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} shader_uniforms;
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static Math::Vec4<float24> vs_default_attributes[16];
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// TODO: Not sure where the shader binary and swizzle patterns are supposed to be loaded to!
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// For now, we just keep these local arrays around.
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static std::array<u32, 1024> shader_memory;
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@ -60,6 +62,10 @@ Math::Vec4<u8>& GetIntUniform(u32 index) {
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return shader_uniforms.i[index];
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}
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Math::Vec4<float24>& GetDefaultAttribute(u32 index) {
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return vs_default_attributes[index];
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}
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const std::array<u32, 1024>& GetShaderBinary() {
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return shader_memory;
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}
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@ -568,22 +574,23 @@ OutputVertex RunShader(const InputVertex& input, int num_attributes) {
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const auto& attribute_register_map = registers.vs_input_register_map;
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float24 dummy_register;
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boost::fill(state.input_register_table, &dummy_register);
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if(num_attributes > 0) state.input_register_table[attribute_register_map.attribute0_register] = &input.attr[0].x;
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if(num_attributes > 1) state.input_register_table[attribute_register_map.attribute1_register] = &input.attr[1].x;
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if(num_attributes > 2) state.input_register_table[attribute_register_map.attribute2_register] = &input.attr[2].x;
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if(num_attributes > 3) state.input_register_table[attribute_register_map.attribute3_register] = &input.attr[3].x;
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if(num_attributes > 4) state.input_register_table[attribute_register_map.attribute4_register] = &input.attr[4].x;
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if(num_attributes > 5) state.input_register_table[attribute_register_map.attribute5_register] = &input.attr[5].x;
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if(num_attributes > 6) state.input_register_table[attribute_register_map.attribute6_register] = &input.attr[6].x;
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if(num_attributes > 7) state.input_register_table[attribute_register_map.attribute7_register] = &input.attr[7].x;
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if(num_attributes > 8) state.input_register_table[attribute_register_map.attribute8_register] = &input.attr[8].x;
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if(num_attributes > 9) state.input_register_table[attribute_register_map.attribute9_register] = &input.attr[9].x;
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if(num_attributes > 10) state.input_register_table[attribute_register_map.attribute10_register] = &input.attr[10].x;
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if(num_attributes > 11) state.input_register_table[attribute_register_map.attribute11_register] = &input.attr[11].x;
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if(num_attributes > 12) state.input_register_table[attribute_register_map.attribute12_register] = &input.attr[12].x;
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if(num_attributes > 13) state.input_register_table[attribute_register_map.attribute13_register] = &input.attr[13].x;
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if(num_attributes > 14) state.input_register_table[attribute_register_map.attribute14_register] = &input.attr[14].x;
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if(num_attributes > 15) state.input_register_table[attribute_register_map.attribute15_register] = &input.attr[15].x;
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if (num_attributes > 0) state.input_register_table[attribute_register_map.attribute0_register] = &input.attr[0].x;
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if (num_attributes > 1) state.input_register_table[attribute_register_map.attribute1_register] = &input.attr[1].x;
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if (num_attributes > 2) state.input_register_table[attribute_register_map.attribute2_register] = &input.attr[2].x;
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if (num_attributes > 3) state.input_register_table[attribute_register_map.attribute3_register] = &input.attr[3].x;
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if (num_attributes > 4) state.input_register_table[attribute_register_map.attribute4_register] = &input.attr[4].x;
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if (num_attributes > 5) state.input_register_table[attribute_register_map.attribute5_register] = &input.attr[5].x;
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if (num_attributes > 6) state.input_register_table[attribute_register_map.attribute6_register] = &input.attr[6].x;
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if (num_attributes > 7) state.input_register_table[attribute_register_map.attribute7_register] = &input.attr[7].x;
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if (num_attributes > 8) state.input_register_table[attribute_register_map.attribute8_register] = &input.attr[8].x;
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if (num_attributes > 9) state.input_register_table[attribute_register_map.attribute9_register] = &input.attr[9].x;
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if (num_attributes > 10) state.input_register_table[attribute_register_map.attribute10_register] = &input.attr[10].x;
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if (num_attributes > 11) state.input_register_table[attribute_register_map.attribute11_register] = &input.attr[11].x;
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if (num_attributes > 12) state.input_register_table[attribute_register_map.attribute12_register] = &input.attr[12].x;
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if (num_attributes > 13) state.input_register_table[attribute_register_map.attribute13_register] = &input.attr[13].x;
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if (num_attributes > 14) state.input_register_table[attribute_register_map.attribute14_register] = &input.attr[14].x;
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if (num_attributes > 15) state.input_register_table[attribute_register_map.attribute15_register] = &input.attr[15].x;
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state.conditional_code[0] = false;
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state.conditional_code[1] = false;
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@ -74,6 +74,7 @@ OutputVertex RunShader(const InputVertex& input, int num_attributes);
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Math::Vec4<float24>& GetFloatUniform(u32 index);
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bool& GetBoolUniform(u32 index);
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Math::Vec4<u8>& GetIntUniform(u32 index);
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Math::Vec4<float24>& GetDefaultAttribute(u32 index);
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const std::array<u32, 1024>& GetShaderBinary();
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const std::array<u32, 1024>& GetSwizzlePatterns();
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