forked from suyu/suyu
renderer_(opengl/vulkan): Fix tessellation clockwise parameter
This should be assigned CW only on Triangles_CW rather than not Triangles_CCW, making CCW the default winding order rather than CW.
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26b76d2eaf
commit
d3114c620d
3 changed files with 6 additions and 6 deletions
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@ -390,7 +390,7 @@ public:
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FractionalEven = 2,
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};
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enum class OutputPrimitves : u32 {
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enum class OutputPrimitives : u32 {
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Points = 0,
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Lines = 1,
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Triangles_CW = 2,
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@ -401,7 +401,7 @@ public:
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union {
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BitField<0, 2, DomainType> domain_type;
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BitField<4, 2, Spacing> spacing;
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BitField<8, 2, OutputPrimitves> output_primitives;
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BitField<8, 2, OutputPrimitives> output_primitives;
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};
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} params;
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@ -317,8 +317,8 @@ GraphicsPipeline* ShaderCache::CurrentGraphicsPipeline() {
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graphics_key.tessellation_primitive.Assign(regs.tessellation.params.domain_type.Value());
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graphics_key.tessellation_spacing.Assign(regs.tessellation.params.spacing.Value());
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graphics_key.tessellation_clockwise.Assign(
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regs.tessellation.params.output_primitives.Value() !=
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Maxwell::Tessellation::OutputPrimitves::Triangles_CCW);
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regs.tessellation.params.output_primitives.Value() ==
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Maxwell::Tessellation::OutputPrimitives::Triangles_CW);
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graphics_key.xfb_enabled.Assign(regs.transform_feedback_enabled != 0 ? 1 : 0);
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if (graphics_key.xfb_enabled) {
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SetXfbState(graphics_key.xfb_state, regs);
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@ -73,8 +73,8 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
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patch_control_points_minus_one.Assign(regs.patch_vertices - 1);
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tessellation_primitive.Assign(static_cast<u32>(regs.tessellation.params.domain_type.Value()));
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tessellation_spacing.Assign(static_cast<u32>(regs.tessellation.params.spacing.Value()));
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tessellation_clockwise.Assign(regs.tessellation.params.output_primitives.Value() !=
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Maxwell::Tessellation::OutputPrimitves::Triangles_CCW);
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tessellation_clockwise.Assign(regs.tessellation.params.output_primitives.Value() ==
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Maxwell::Tessellation::OutputPrimitives::Triangles_CW);
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logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0);
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logic_op.Assign(PackLogicOp(regs.logic_op.op));
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topology.Assign(regs.draw.topology);
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