forked from suyu/suyu
shader: Implement OUT
This commit is contained in:
ReinUsesLisp
ameerj
parent
dd3432d357
commit
a6cef71cc0
10 changed files with 73 additions and 17 deletions
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@ -134,6 +134,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/move_register_to_predicate.cpp
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frontend/maxwell/translate/impl/move_special_register.cpp
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frontend/maxwell/translate/impl/not_implemented.cpp
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frontend/maxwell/translate/impl/output_geometry.cpp
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frontend/maxwell/translate/impl/predicate_set_predicate.cpp
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frontend/maxwell/translate/impl/predicate_set_register.cpp
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frontend/maxwell/translate/impl/select_source_with_predicate.cpp
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@ -34,6 +34,8 @@ void EmitMemoryBarrierDeviceLevel(EmitContext& ctx);
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void EmitMemoryBarrierSystemLevel(EmitContext& ctx);
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void EmitPrologue(EmitContext& ctx);
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void EmitEpilogue(EmitContext& ctx);
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void EmitEmitVertex(EmitContext& ctx, Id stream);
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void EmitEndPrimitive(EmitContext& ctx, Id stream);
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void EmitGetRegister(EmitContext& ctx);
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void EmitSetRegister(EmitContext& ctx);
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void EmitGetPred(EmitContext& ctx);
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@ -36,4 +36,12 @@ void EmitEpilogue(EmitContext& ctx) {
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}
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}
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void EmitEmitVertex(EmitContext& ctx, Id stream) {
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ctx.OpEmitStreamVertex(stream);
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}
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void EmitEndPrimitive(EmitContext& ctx, Id stream) {
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ctx.OpEndStreamPrimitive(stream);
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}
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} // namespace Shader::Backend::SPIRV
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@ -125,6 +125,14 @@ void IREmitter::Epilogue() {
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Inst(Opcode::Epilogue);
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}
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void IREmitter::EmitVertex(const U32& stream) {
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Inst(Opcode::EmitVertex, stream);
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}
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void IREmitter::EndPrimitive(const U32& stream) {
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Inst(Opcode::EndPrimitive, stream);
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}
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U32 IREmitter::GetReg(IR::Reg reg) {
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return Inst<U32>(Opcode::GetRegister, reg);
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}
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@ -43,6 +43,9 @@ public:
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void Prologue();
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void Epilogue();
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void EmitVertex(const U32& stream);
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void EndPrimitive(const U32& stream);
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[[nodiscard]] U32 GetReg(IR::Reg reg);
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void SetReg(IR::Reg reg, const U32& value);
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@ -69,6 +69,8 @@ bool Inst::MayHaveSideEffects() const noexcept {
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case Opcode::MemoryBarrierSystemLevel:
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case Opcode::Prologue:
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case Opcode::Epilogue:
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case Opcode::EmitVertex:
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case Opcode::EndPrimitive:
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case Opcode::SetAttribute:
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case Opcode::SetAttributeIndexed:
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case Opcode::SetFragColor:
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@ -25,6 +25,8 @@ OPCODE(MemoryBarrierSystemLevel, Void,
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// Special operations
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OPCODE(Prologue, Void, )
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OPCODE(Epilogue, Void, )
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OPCODE(EmitVertex, Void, U32, )
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OPCODE(EndPrimitive, Void, U32, )
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// Context getters/setters
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OPCODE(GetRegister, U32, Reg, )
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@ -64,7 +64,7 @@ void TranslatorVisitor::ALD(u64 insn) {
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BitField<8, 8, IR::Reg> index_reg;
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BitField<20, 10, u64> absolute_offset;
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BitField<20, 11, s64> relative_offset;
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BitField<39, 8, IR::Reg> stream_reg;
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BitField<39, 8, IR::Reg> array_reg;
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BitField<32, 1, u64> o;
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BitField<31, 1, u64> patch;
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BitField<47, 2, Size> size;
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@ -100,16 +100,13 @@ void TranslatorVisitor::AST(u64 insn) {
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BitField<20, 10, u64> absolute_offset;
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BitField<20, 11, s64> relative_offset;
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BitField<31, 1, u64> patch;
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BitField<39, 8, IR::Reg> stream_reg;
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BitField<39, 8, IR::Reg> array_reg;
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BitField<47, 2, Size> size;
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} const ast{insn};
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if (ast.patch != 0) {
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throw NotImplementedException("P");
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}
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if (ast.stream_reg != IR::Reg::RZ) {
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throw NotImplementedException("Stream store");
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}
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if (ast.index_reg != IR::Reg::RZ) {
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throw NotImplementedException("Indexed store");
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}
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@ -169,18 +169,6 @@ void TranslatorVisitor::NOP(u64) {
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// NOP is No-Op.
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}
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void TranslatorVisitor::OUT_reg(u64) {
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ThrowNotImplemented(Opcode::OUT_reg);
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}
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void TranslatorVisitor::OUT_cbuf(u64) {
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ThrowNotImplemented(Opcode::OUT_cbuf);
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}
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void TranslatorVisitor::OUT_imm(u64) {
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ThrowNotImplemented(Opcode::OUT_imm);
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}
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void TranslatorVisitor::PBK() {
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// PBK is a no-op
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}
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@ -0,0 +1,45 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void OUT(TranslatorVisitor& v, u64 insn, IR::U32 stream_index) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> output_reg; // Not needed on host
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BitField<39, 1, u64> emit;
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BitField<40, 1, u64> cut;
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} const out{insn};
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stream_index = v.ir.BitwiseAnd(stream_index, v.ir.Imm32(0b11));
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if (out.emit != 0) {
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v.ir.EmitVertex(stream_index);
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}
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if (out.cut != 0) {
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v.ir.EndPrimitive(stream_index);
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}
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// Host doesn't need the output register, but we can write to it to avoid undefined reads
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v.X(out.dest_reg, v.ir.Imm32(0));
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}
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} // Anonymous namespace
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void TranslatorVisitor::OUT_reg(u64 insn) {
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OUT(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::OUT_cbuf(u64 insn) {
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OUT(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::OUT_imm(u64 insn) {
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OUT(*this, insn, GetImm20(insn));
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}
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} // namespace Shader::Maxwell
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