forked from suyu/suyu
gl_shader_decompiler: Implement FMUL/FADD/FFMA immediate instructions.
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8d4899d6ea
commit
5a28dce9eb
2 changed files with 53 additions and 12 deletions
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@ -4,6 +4,7 @@
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#pragma once
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#include <cstring>
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#include <map>
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#include <string>
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#include "common/bit_field.h"
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@ -289,6 +290,7 @@ enum class SubOp : u64 {
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Lg2 = 0x3,
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Rcp = 0x4,
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Rsq = 0x5,
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Min = 0x8,
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};
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union Instruction {
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@ -307,11 +309,22 @@ union Instruction {
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BitField<39, 8, Register> gpr39;
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union {
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BitField<20, 19, u64> imm20;
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BitField<45, 1, u64> negate_b;
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BitField<46, 1, u64> abs_a;
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BitField<48, 1, u64> negate_a;
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BitField<49, 1, u64> abs_b;
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BitField<50, 1, u64> abs_d;
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BitField<56, 1, u64> negate_imm;
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float GetImm20() const {
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float result{};
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u32 imm{static_cast<u32>(imm20)};
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imm <<= 12;
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imm |= negate_imm ? 0x80000000 : 0;
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std::memcpy(&result, &imm, sizeof(imm));
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return result;
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}
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} alu;
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union {
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@ -319,6 +332,7 @@ union Instruction {
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BitField<49, 1, u64> negate_c;
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} ffma;
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BitField<61, 1, u64> is_b_imm;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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@ -190,6 +190,11 @@ private:
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}
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}
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/// Generates code representing an immediate value
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static std::string GetImmediate(const Instruction& instr) {
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return std::to_string(instr.alu.GetImm20());
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}
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/// Generates code representing a temporary (GPR) register.
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std::string GetRegister(const Register& reg, unsigned elem = 0) {
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment && reg < 4) {
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@ -269,24 +274,32 @@ private:
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}
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std::string op_b = instr.alu.negate_b ? "-" : "";
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if (instr.is_b_imm) {
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op_b += GetImmediate(instr);
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} else {
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if (instr.is_b_gpr) {
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op_b += GetRegister(instr.gpr20);
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} else {
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op_b += GetUniform(instr.uniform);
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}
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}
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if (instr.alu.abs_b) {
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op_b = "abs(" + op_b + ")";
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}
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::FMUL_C:
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case OpCode::Id::FMUL_R: {
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SetDest(0, dest, op_a + " * " + op_b, 1, 1);
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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SetDest(0, dest, op_a + " * " + op_b, 1, 1, instr.alu.abs_d);
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break;
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}
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case OpCode::Id::FADD_C:
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case OpCode::Id::FADD_R: {
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SetDest(0, dest, op_a + " + " + op_b, 1, 1);
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case OpCode::Id::FADD_R:
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case OpCode::Id::FADD_IMM: {
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SetDest(0, dest, op_a + " + " + op_b, 1, 1, instr.alu.abs_d);
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break;
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}
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case OpCode::Id::MUFU: {
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@ -316,16 +329,28 @@ private:
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std::string dest = GetRegister(instr.gpr0);
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std::string op_a = GetRegister(instr.gpr8);
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std::string op_b = instr.ffma.negate_b ? "-" : "";
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op_b += GetUniform(instr.uniform);
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std::string op_c = instr.ffma.negate_c ? "-" : "";
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op_c += GetRegister(instr.gpr39);
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::FFMA_CR: {
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SetDest(0, dest, op_a + " * " + op_b + " + " + op_c, 1, 1);
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op_b += GetUniform(instr.uniform);
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op_c += GetRegister(instr.gpr39);
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break;
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}
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case OpCode::Id::FFMA_RR: {
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op_b += GetRegister(instr.gpr20);
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op_c += GetRegister(instr.gpr39);
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break;
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}
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case OpCode::Id::FFMA_RC: {
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op_b += GetRegister(instr.gpr39);
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op_c += GetUniform(instr.uniform);
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break;
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}
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case OpCode::Id::FFMA_IMM: {
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op_b += GetImmediate(instr);
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op_c += GetRegister(instr.gpr39);
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break;
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}
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default: {
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@ -336,6 +361,8 @@ private:
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break;
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}
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}
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SetDest(0, dest, op_a + " * " + op_b + " + " + op_c, 1, 1);
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break;
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}
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case OpCode::Type::Memory: {
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