forked from suyu/suyu
Fix stencil func registers, make clip control equivalent to how it was before, but surely wrong.
This commit is contained in:
parent
c3cae9d992
commit
4496030ea9
8 changed files with 51 additions and 44 deletions
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@ -61,7 +61,7 @@ void SetupDirtyRenderTargets(Maxwell3D::DirtyState::Tables& tables) {
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}
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void SetupDirtyShaders(Maxwell3D::DirtyState::Tables& tables) {
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FillBlock(tables[0], OFF(pipelines), NUM(pipelines) * Maxwell3D::Regs::MaxShaderProgram,
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FillBlock(tables[0], OFF(pipelines), NUM(pipelines[0]) * Maxwell3D::Regs::MaxShaderProgram,
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Shaders);
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}
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} // Anonymous namespace
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@ -74,15 +74,15 @@ void Maxwell3D::InitializeRegisterDefaults() {
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regs.stencil_front_op.zfail = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_front_op.zpass = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_front_op.func = Regs::ComparisonOp::Always_GL;
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regs.stencil_front_func.func_mask = 0xFFFFFFFF;
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regs.stencil_front_func.mask = 0xFFFFFFFF;
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regs.stencil_front_func_mask = 0xFFFFFFFF;
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regs.stencil_front_mask = 0xFFFFFFFF;
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regs.stencil_two_side_enable = 1;
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regs.stencil_back_op.fail = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_back_op.zfail = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_back_op.zpass = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_back_op.func = Regs::ComparisonOp::Always_GL;
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regs.stencil_back_func.func_mask = 0xFFFFFFFF;
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regs.stencil_back_func.mask = 0xFFFFFFFF;
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regs.stencil_back_func_mask = 0xFFFFFFFF;
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regs.stencil_back_mask = 0xFFFFFFFF;
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regs.depth_test_func = Regs::ComparisonOp::Always_GL;
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regs.gl_front_face = Regs::FrontFace::CounterClockWise;
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@ -1795,12 +1795,6 @@ public:
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ComparisonOp func;
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};
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struct StencilFunc {
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s32 ref;
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u32 func_mask;
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u32 mask;
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};
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struct PsSaturate {
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// Opposite of DepthMode
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enum class Depth : u32 {
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@ -2737,7 +2731,9 @@ public:
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u32 post_z_pixel_imask; ///< 0x0F1C
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INSERT_PADDING_BYTES_NOINIT(0x20);
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ConstantColorRendering const_color_rendering; ///< 0x0F40
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StencilFunc stencil_back_func; ///< 0x0F54
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s32 stencil_back_ref; ///< 0x0F54
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u32 stencil_back_mask; ///< 0x0F58
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u32 stencil_back_func_mask; ///< 0x0F5C
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INSERT_PADDING_BYTES_NOINIT(0x24);
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VertexStreamSubstitute vertex_stream_substitute; ///< 0x0F84
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u32 line_mode_clip_generated_edge_do_not_draw; ///< 0x0F8C
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@ -2855,7 +2851,9 @@ public:
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Blend blend; ///< 0x133C
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u32 stencil_enable; ///< 0x1380
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StencilOp stencil_front_op; ///< 0x1384
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StencilFunc stencil_front_func; ///< 0x1394
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s32 stencil_front_ref; ///< 0x1394
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s32 stencil_front_func_mask; ///< 0x1398
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s32 stencil_front_mask; ///< 0x139C
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INSERT_PADDING_BYTES_NOINIT(0x4);
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u32 draw_auto_start_byte_count; ///< 0x13A4
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PsSaturate frag_color_clamp; ///< 0x13A8
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@ -3311,7 +3309,9 @@ ASSERT_REG_POSITION(vpc_perf, 0x0F14);
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ASSERT_REG_POSITION(pm_local_trigger, 0x0F18);
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ASSERT_REG_POSITION(post_z_pixel_imask, 0x0F1C);
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ASSERT_REG_POSITION(const_color_rendering, 0x0F40);
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ASSERT_REG_POSITION(stencil_back_func, 0x0F54);
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ASSERT_REG_POSITION(stencil_back_ref, 0x0F54);
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ASSERT_REG_POSITION(stencil_back_mask, 0x0F58);
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ASSERT_REG_POSITION(stencil_back_func_mask, 0x0F5C);
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ASSERT_REG_POSITION(vertex_stream_substitute, 0x0F84);
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ASSERT_REG_POSITION(line_mode_clip_generated_edge_do_not_draw, 0x0F8C);
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ASSERT_REG_POSITION(color_mask_common, 0x0F90);
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@ -3416,7 +3416,9 @@ ASSERT_REG_POSITION(invalidate_texture_data_cache_lines, 0x1338);
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ASSERT_REG_POSITION(blend, 0x133C);
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ASSERT_REG_POSITION(stencil_enable, 0x1380);
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ASSERT_REG_POSITION(stencil_front_op, 0x1384);
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ASSERT_REG_POSITION(stencil_front_func, 0x1394);
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ASSERT_REG_POSITION(stencil_front_ref, 0x1394);
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ASSERT_REG_POSITION(stencil_front_func_mask, 0x1398);
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ASSERT_REG_POSITION(stencil_front_mask, 0x139C);
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ASSERT_REG_POSITION(draw_auto_start_byte_count, 0x13A4);
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ASSERT_REG_POSITION(frag_color_clamp, 0x13A8);
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ASSERT_REG_POSITION(window_origin, 0x13AC);
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@ -658,8 +658,13 @@ void RasterizerOpenGL::SyncDepthClamp() {
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}
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flags[Dirty::DepthClampEnabled] = false;
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oglEnable(GL_DEPTH_CLAMP, maxwell3d->regs.viewport_clip_control.geometry_clip !=
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Maxwell::ViewportClipControl::GeometryClip::Passthrough);
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bool depth_clamp_disabled{maxwell3d->regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::Passthrough ||
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maxwell3d->regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::FrustumXYZ ||
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maxwell3d->regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::FrustumZ};
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oglEnable(GL_DEPTH_CLAMP, !depth_clamp_disabled);
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}
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void RasterizerOpenGL::SyncClipEnabled(u32 clip_mask) {
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@ -746,19 +751,19 @@ void RasterizerOpenGL::SyncStencilTestState() {
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oglEnable(GL_STENCIL_TEST, regs.stencil_enable);
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glStencilFuncSeparate(GL_FRONT, MaxwellToGL::ComparisonOp(regs.stencil_front_op.func),
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regs.stencil_front_func.ref, regs.stencil_front_func.func_mask);
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regs.stencil_front_ref, regs.stencil_front_func_mask);
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glStencilOpSeparate(GL_FRONT, MaxwellToGL::StencilOp(regs.stencil_front_op.fail),
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MaxwellToGL::StencilOp(regs.stencil_front_op.zfail),
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MaxwellToGL::StencilOp(regs.stencil_front_op.zpass));
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glStencilMaskSeparate(GL_FRONT, regs.stencil_front_func.mask);
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glStencilMaskSeparate(GL_FRONT, regs.stencil_front_mask);
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if (regs.stencil_two_side_enable) {
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glStencilFuncSeparate(GL_BACK, MaxwellToGL::ComparisonOp(regs.stencil_back_op.func),
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regs.stencil_back_func.ref, regs.stencil_back_func.mask);
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regs.stencil_back_ref, regs.stencil_back_mask);
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glStencilOpSeparate(GL_BACK, MaxwellToGL::StencilOp(regs.stencil_back_op.fail),
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MaxwellToGL::StencilOp(regs.stencil_back_op.zfail),
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MaxwellToGL::StencilOp(regs.stencil_back_op.zpass));
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glStencilMaskSeparate(GL_BACK, regs.stencil_back_func.mask);
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glStencilMaskSeparate(GL_BACK, regs.stencil_back_mask);
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} else {
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glStencilFuncSeparate(GL_BACK, GL_ALWAYS, 0, 0xFFFFFFFF);
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glStencilOpSeparate(GL_BACK, GL_KEEP, GL_KEEP, GL_KEEP);
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@ -100,14 +100,12 @@ void SetupDirtyDepthTest(Tables& tables) {
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void SetupDirtyStencilTest(Tables& tables) {
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static constexpr std::array offsets = {
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OFF(stencil_enable), OFF(stencil_front_op.func),
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OFF(stencil_front_func.ref), OFF(stencil_front_func.func_mask),
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OFF(stencil_front_op.fail), OFF(stencil_front_op.zfail),
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OFF(stencil_front_op.zpass), OFF(stencil_front_func.mask),
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OFF(stencil_two_side_enable), OFF(stencil_back_op.func),
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OFF(stencil_back_func.ref), OFF(stencil_back_func.func_mask),
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OFF(stencil_back_op.fail), OFF(stencil_back_op.zfail),
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OFF(stencil_back_op.zpass), OFF(stencil_back_func.mask)};
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OFF(stencil_enable), OFF(stencil_front_op.func), OFF(stencil_front_ref),
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OFF(stencil_front_func_mask), OFF(stencil_front_op.fail), OFF(stencil_front_op.zfail),
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OFF(stencil_front_op.zpass), OFF(stencil_front_mask), OFF(stencil_two_side_enable),
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OFF(stencil_back_op.func), OFF(stencil_back_ref), OFF(stencil_back_func_mask),
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OFF(stencil_back_op.fail), OFF(stencil_back_op.zfail), OFF(stencil_back_op.zpass),
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OFF(stencil_back_mask)};
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for (const auto offset : offsets) {
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tables[0][offset] = StencilTest;
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}
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@ -63,7 +63,11 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
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primitive_restart_enable.Assign(regs.primitive_restart.enabled != 0 ? 1 : 0);
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depth_bias_enable.Assign(enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]] != 0 ? 1 : 0);
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depth_clamp_disabled.Assign(regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::Passthrough);
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Maxwell::ViewportClipControl::GeometryClip::Passthrough ||
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regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::FrustumXYZ ||
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regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::FrustumZ);
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ndc_minus_one_to_one.Assign(regs.depth_mode == Maxwell::DepthMode::MinusOneToOne ? 1 : 0);
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polygon_mode.Assign(PackPolygonMode(regs.polygon_mode_front));
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patch_control_points_minus_one.Assign(regs.patch_vertices - 1);
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@ -772,11 +772,10 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs)
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if (regs.stencil_two_side_enable) {
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// Separate values per face
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scheduler.Record(
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[front_ref = regs.stencil_front_func.ref,
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front_write_mask = regs.stencil_front_func.mask,
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front_test_mask = regs.stencil_front_func.func_mask,
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back_ref = regs.stencil_back_func.ref, back_write_mask = regs.stencil_back_func.mask,
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back_test_mask = regs.stencil_back_func.func_mask](vk::CommandBuffer cmdbuf) {
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[front_ref = regs.stencil_front_ref, front_write_mask = regs.stencil_front_mask,
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front_test_mask = regs.stencil_front_func_mask, back_ref = regs.stencil_back_ref,
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back_write_mask = regs.stencil_back_mask,
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back_test_mask = regs.stencil_back_func_mask](vk::CommandBuffer cmdbuf) {
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// Front face
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cmdbuf.SetStencilReference(VK_STENCIL_FACE_FRONT_BIT, front_ref);
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cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_FRONT_BIT, front_write_mask);
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@ -789,9 +788,8 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs)
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});
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} else {
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// Front face defines both faces
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scheduler.Record([ref = regs.stencil_front_func.ref,
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write_mask = regs.stencil_front_func.mask,
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test_mask = regs.stencil_front_func.func_mask](vk::CommandBuffer cmdbuf) {
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scheduler.Record([ref = regs.stencil_front_ref, write_mask = regs.stencil_front_mask,
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test_mask = regs.stencil_front_func_mask](vk::CommandBuffer cmdbuf) {
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cmdbuf.SetStencilReference(VK_STENCIL_FACE_FRONT_AND_BACK, ref);
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cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_FRONT_AND_BACK, write_mask);
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cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_FRONT_AND_BACK, test_mask);
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@ -77,12 +77,12 @@ void SetupDirtyDepthBounds(Tables& tables) {
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void SetupDirtyStencilProperties(Tables& tables) {
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auto& table = tables[0];
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table[OFF(stencil_two_side_enable)] = StencilProperties;
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table[OFF(stencil_front_func.ref)] = StencilProperties;
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table[OFF(stencil_front_func.mask)] = StencilProperties;
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table[OFF(stencil_front_func.func_mask)] = StencilProperties;
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table[OFF(stencil_back_func.ref)] = StencilProperties;
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table[OFF(stencil_back_func.mask)] = StencilProperties;
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table[OFF(stencil_back_func.func_mask)] = StencilProperties;
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table[OFF(stencil_front_ref)] = StencilProperties;
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table[OFF(stencil_front_mask)] = StencilProperties;
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table[OFF(stencil_front_func_mask)] = StencilProperties;
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table[OFF(stencil_back_ref)] = StencilProperties;
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table[OFF(stencil_back_mask)] = StencilProperties;
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table[OFF(stencil_back_func_mask)] = StencilProperties;
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}
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void SetupDirtyLineWidth(Tables& tables) {
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