90 lines
2.9 KiB
Nix
90 lines
2.9 KiB
Nix
{ stdenv, fetchFromGitHub
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, pkgconfig, bison, flex
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, tcl, readline, libffi, python3
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, protobuf, zlib
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, verilog
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}:
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with builtins;
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stdenv.mkDerivation rec {
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pname = "yosys";
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version = "2019.10.18";
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srcs = [
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(fetchFromGitHub {
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owner = "yosyshq";
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repo = "yosys";
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rev = "3c41599ee1f62e4d77ba630fa1a245ef3fe236fa";
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sha256 = "0jg2g8v08ax1q6qlvn8c1h147m03adzrgf21043xwbh4c7s5k137";
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name = "yosys";
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})
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# NOTE: the version of abc used here is synchronized with
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# the one in the yosys Makefile of the version above;
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# keep them the same for quality purposes.
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(fetchFromGitHub {
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owner = "berkeley-abc";
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repo = "abc";
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rev = "623b5e82513d076a19f864c01930ad1838498894";
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sha256 = "1mrfqwsivflqdzc3531r6mzp33dfyl6dnqjdwfcq137arqh36m67";
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name = "yosys-abc";
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})
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];
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sourceRoot = "yosys";
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enableParallelBuilding = true;
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nativeBuildInputs = [ pkgconfig ];
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buildInputs = [ tcl readline libffi python3 bison flex protobuf zlib ];
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makeFlags = [ "ENABLE_PROTOBUF=1" ];
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patchPhase = ''
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substituteInPlace ../yosys-abc/Makefile \
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--replace 'CC := gcc' "" \
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--replace 'CXX := g++' ""
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substituteInPlace ./Makefile \
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--replace 'CXX = clang' "" \
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--replace 'LD = clang++' 'LD = $(CXX)' \
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--replace 'CXX = gcc' "" \
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--replace 'LD = gcc' 'LD = $(CXX)' \
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--replace 'ABCMKARGS = CC="$(CXX)" CXX="$(CXX)"' 'ABCMKARGS =' \
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--replace 'echo UNKNOWN' 'echo ${substring 0 10 (elemAt srcs 0).rev}'
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patchShebangs tests
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'';
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preBuild = ''
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chmod -R u+w ../yosys-abc
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ln -s ../yosys-abc abc
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make config-${if stdenv.cc.isClang or false then "clang" else "gcc"}
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echo 'ABCREV := default' >> Makefile.conf
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makeFlags="PREFIX=$out $makeFlags"
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# we have to do this ourselves for some reason...
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(cd misc && ${protobuf}/bin/protoc --cpp_out ../backends/protobuf/ ./yosys.proto)
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'';
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doCheck = true;
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checkInputs = [ verilog ];
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# checkPhase defaults to VERBOSE=y, which gets passed down to abc,
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# which then does $(VERBOSE)gcc, which then complains about not
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# being able to find ygcc. Life is pain.
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checkFlags = [ " " ];
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meta = {
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description = "Framework for RTL synthesis tools";
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longDescription = ''
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Yosys is a framework for RTL synthesis tools. It currently has
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extensive Verilog-2005 support and provides a basic set of
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synthesis algorithms for various application domains.
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Yosys can be adapted to perform any synthesis job by combining
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the existing passes (algorithms) using synthesis scripts and
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adding additional passes as needed by extending the yosys C++
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code base.
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'';
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homepage = http://www.clifford.at/yosys/;
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license = stdenv.lib.licenses.isc;
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maintainers = with stdenv.lib.maintainers; [ shell thoughtpolice emily ];
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platforms = stdenv.lib.platforms.all;
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};
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}
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