207 lines
7.7 KiB
Diff
207 lines
7.7 KiB
Diff
http://gentoo-overlays.zugaina.org/loongson/portage/net-libs/xulrunner/files/xulrunner-chromium-mips.patch
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diff --git a/ipc/chromium/src/base/atomicops.h b/ipc/chromium/src/base/atomicops.h
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index 87df918..363bf63 100644
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--- a/ipc/chromium/src/base/atomicops.h
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+++ b/ipc/chromium/src/base/atomicops.h
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@@ -132,6 +132,8 @@ Atomic64 Release_Load(volatile const Atomic64* ptr);
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#include "base/atomicops_internals_x86_gcc.h"
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#elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY)
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#include "base/atomicops_internals_arm_gcc.h"
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+#elif defined(COMPILER_GCC) && defined(ARCH_CPU_MIPS_FAMILY)
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+#include "base/atomicops_internals_mips_gcc.h"
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#else
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#error "Atomic operations are not supported on your platform"
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#endif
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diff --git a/ipc/chromium/src/base/atomicops_internals_mips_gcc.h b/ipc/chromium/src/base/atomicops_internals_mips_gcc.h
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new file mode 100644
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index 0000000..d1b87ee
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--- /dev/null
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+++ b/ipc/chromium/src/base/atomicops_internals_mips_gcc.h
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@@ -0,0 +1,160 @@
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+// Copyright (c) 2010 Zhang, Le <r0bertz@gentoo.org>
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+// Use of this source code is governed by GPLv2.
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+
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+// This file is an internal atomic implementation, use base/atomicops.h instead.
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+
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+#ifndef BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_
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+#define BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_
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+
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+#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
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+
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+namespace base {
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+namespace subtle {
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+
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+// 32-bit low-level operations on any platform.
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+
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+inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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+ Atomic32 old_value,
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+ Atomic32 new_value) {
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+ Atomic32 prev;
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+ __asm__ __volatile__(
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+ " .set push \n"
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+ " .set noat \n"
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+ " .set mips3 \n"
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+ "1: ll %0, %2 \n"
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+ " bne %0, %z3, 2f \n"
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+ " .set mips0 \n"
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+ " move $1, %z4 \n"
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+ " .set mips3 \n"
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+ " sc $1, %1 \n"
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+ " beqz $1, 3f \n"
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+ "2: \n"
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+ " .subsection 2 \n"
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+ "3: b 1b \n"
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+ " .previous \n"
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+ " .set pop \n"
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+ : "=&r" (prev), "=R" (*ptr)
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+ : "R" (*ptr), "Jr" (old_value), "Jr" (new_value)
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+ : "memory");
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+ return prev;
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+}
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+
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+inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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+ Atomic32 new_value) {
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+ unsigned int ret_value;
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+ unsigned long dummy;
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+
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+ __asm__ __volatile__(" .set mips3 \n"
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+ "1: ll %0, %3 # xchg_u32 \n"
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+ " .set mips0 \n"
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+ " move %2, %z4 \n"
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+ " .set mips3 \n"
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+ " sc %2, %1 \n"
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+ " beqz %2, 2f \n"
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+ " .subsection 2 \n"
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+ "2: b 1b \n"
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+ " .previous \n"
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+ " .set mips0 \n"
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+ : "=&r" (ret_value), "=m" (*ptr), "=&r" (dummy)
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+ : "R" (*ptr), "Jr" (new_value)
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+ : "memory");
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+
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+ return ret_value; // Now it's the previous value.
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+}
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+
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+inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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+ Atomic32 increment) {
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+ Atomic32 temp, result;
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+ __asm__ __volatile__(
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+ " .set mips3 \n"
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+ "1: ll %1, %2 # atomic_add_return \n"
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+ " addu %0, %1, %3 \n"
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+ " sc %0, %2 \n"
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+ " beqz %0, 2f \n"
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+ " addu %0, %1, %3 \n"
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+ " .subsection 2 \n"
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+ "2: b 1b \n"
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+ " .previous \n"
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+ " .set mips0 \n"
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+ : "=&r" (result), "=&r" (temp), "=m" (*ptr)
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+ : "Ir" (increment), "m" (*ptr)
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+ : "memory");
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+ return result;
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+}
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+
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+inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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+ Atomic32 increment) {
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+ Atomic32 temp, result;
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+ __asm__ __volatile__(
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+ " .set mips3 \n"
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+ "1: ll %1, %2 # atomic_add_return \n"
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+ " addu %0, %1, %3 \n"
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+ " sc %0, %2 \n"
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+ " beqz %0, 2f \n"
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+ " addu %0, %1, %3 \n"
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+ " .subsection 2 \n"
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+ "2: b 1b \n"
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+ " .previous \n"
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+ " .set mips0 \n"
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+ : "=&r" (result), "=&r" (temp), "=m" (*ptr)
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+ : "Ir" (increment), "m" (*ptr)
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+ : "memory");
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+ __asm__ __volatile__("sync" : : : "memory");
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+ return result;
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+}
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+
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+inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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+ Atomic32 old_value,
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+ Atomic32 new_value) {
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+ Atomic32 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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+ __asm__ __volatile__("sync" : : : "memory");
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+ return x;
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+}
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+
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+inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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+ Atomic32 old_value,
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+ Atomic32 new_value) {
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+ return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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+}
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+
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+inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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+ *ptr = value;
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+}
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+
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+inline void MemoryBarrier() {
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+ __asm__ __volatile__("sync" : : : "memory");
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+}
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+
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+inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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+ *ptr = value;
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+ __asm__ __volatile__("sync" : : : "memory");
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+}
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+
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+inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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+ ATOMICOPS_COMPILER_BARRIER();
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+ *ptr = value; // An x86 store acts as a release barrier.
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+ // See comments in Atomic64 version of Release_Store(), below.
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+}
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+
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+inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
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+ return *ptr;
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+}
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+
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+inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
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+ Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
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+ // See comments in Atomic64 version of Release_Store(), below.
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+ ATOMICOPS_COMPILER_BARRIER();
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+ return value;
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+}
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+
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+inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
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+ MemoryBarrier();
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+ return *ptr;
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+}
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+
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+} // namespace base::subtle
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+} // namespace base
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+
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+#undef ATOMICOPS_COMPILER_BARRIER
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+
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+#endif // BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_
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diff --git a/ipc/chromium/src/base/debug_util_posix.cc b/ipc/chromium/src/base/debug_util_posix.cc
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index f7c58b4..50fb41d 100644
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--- a/ipc/chromium/src/base/debug_util_posix.cc
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+++ b/ipc/chromium/src/base/debug_util_posix.cc
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@@ -108,7 +108,7 @@ bool DebugUtil::BeingDebugged() {
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// static
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void DebugUtil::BreakDebugger() {
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-#if !defined(ARCH_CPU_ARM_FAMILY)
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+#if !defined(ARCH_CPU_ARM_FAMILY) && !defined(ARCH_CPU_MIPS_FAMILY)
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asm ("int3");
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#endif
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}
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diff --git a/ipc/chromium/src/build/build_config.h b/ipc/chromium/src/build/build_config.h
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index 36f83e7..128bbc7 100644
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--- a/ipc/chromium/src/build/build_config.h
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+++ b/ipc/chromium/src/build/build_config.h
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@@ -57,6 +57,8 @@
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#define ARCH_CPU_ARMEL 1
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#define ARCH_CPU_32_BITS 1
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#define WCHAR_T_IS_UNSIGNED 1
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+#elif defined(__MIPSEL__)
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+#define ARCH_CPU_MIPS_FAMILY 1
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#else
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#error Please add support for your architecture in build/build_config.h
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#endif
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