Merge pull request #173225 from matthuszagh/uhdm
Add systemverilog plugin to yosys
This commit is contained in:
commit
b02d74fb5e
4 changed files with 122 additions and 14 deletions
59
pkgs/applications/science/logic/surelog/default.nix
Normal file
59
pkgs/applications/science/logic/surelog/default.nix
Normal file
|
@ -0,0 +1,59 @@
|
|||
{ lib
|
||||
, stdenv
|
||||
, fetchFromGitHub
|
||||
, cmake
|
||||
, python3
|
||||
, pkg-config
|
||||
, libuuid
|
||||
, openjdk11
|
||||
, gperftools
|
||||
}:
|
||||
|
||||
stdenv.mkDerivation rec {
|
||||
pname = "surelog";
|
||||
version = "1.40";
|
||||
|
||||
src = fetchFromGitHub {
|
||||
owner = "chipsalliance";
|
||||
repo = pname;
|
||||
rev = "v${version}";
|
||||
hash = "sha256-5nhJilFIJJDCnJUEUgyPNtWSQUgWcvM6LDFgFatAl/k=";
|
||||
fetchSubmodules = true;
|
||||
};
|
||||
|
||||
nativeBuildInputs = [
|
||||
cmake
|
||||
pkg-config
|
||||
openjdk11
|
||||
(python3.withPackages (p: with p; [
|
||||
psutil
|
||||
orderedmultidict
|
||||
]))
|
||||
];
|
||||
|
||||
buildInputs = [
|
||||
libuuid
|
||||
gperftools
|
||||
];
|
||||
|
||||
doCheck = true;
|
||||
checkPhase = ''
|
||||
runHook preCheck
|
||||
make -j $NIX_BUILD_CORES UnitTests
|
||||
ctest --output-on-failure
|
||||
runHook postCheck
|
||||
'';
|
||||
|
||||
postInstall = ''
|
||||
mv $out/lib/surelog/* $out/lib/
|
||||
mv $out/lib/pkg $out/lib/surelog/
|
||||
'';
|
||||
|
||||
meta = {
|
||||
description = "SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler";
|
||||
homepage = "https://github.com/chipsalliance/Surelog";
|
||||
license = lib.licenses.asl20;
|
||||
maintainers = with lib.maintainers; [ matthuszagh ];
|
||||
platforms = lib.platforms.linux;
|
||||
};
|
||||
}
|
49
pkgs/applications/science/logic/uhdm/default.nix
Normal file
49
pkgs/applications/science/logic/uhdm/default.nix
Normal file
|
@ -0,0 +1,49 @@
|
|||
{ lib
|
||||
, stdenv
|
||||
, fetchFromGitHub
|
||||
, cmake
|
||||
, python3
|
||||
}:
|
||||
|
||||
stdenv.mkDerivation rec {
|
||||
pname = "UHDM";
|
||||
version = "0.9.1.40";
|
||||
|
||||
src = fetchFromGitHub {
|
||||
owner = "chipsalliance";
|
||||
repo = pname;
|
||||
rev = "v${version}";
|
||||
hash = "sha256-CliKU2WM8B9012aDcS/mTyIf+JcsVsc4uRRi9+FRWbM=";
|
||||
fetchSubmodules = true;
|
||||
};
|
||||
|
||||
nativeBuildInputs = [
|
||||
cmake
|
||||
];
|
||||
|
||||
buildInputs = [
|
||||
(python3.withPackages (p: with p; [ orderedmultidict ]))
|
||||
];
|
||||
|
||||
doCheck = true;
|
||||
checkPhase = "make test";
|
||||
|
||||
postInstall = ''
|
||||
mv $out/lib/uhdm/* $out/lib/
|
||||
rm -rf $out/lib/uhdm
|
||||
'';
|
||||
|
||||
prePatch = ''
|
||||
substituteInPlace CMakeLists.txt --replace \
|
||||
'capnp compile' \
|
||||
'capnp compile --src-prefix=''${GENDIR}/..'
|
||||
'';
|
||||
|
||||
meta = {
|
||||
description = "Universal Hardware Data Model";
|
||||
homepage = "https://github.com/chipsalliance/UHDM";
|
||||
license = lib.licenses.asl20;
|
||||
maintainers = with lib.maintainers; [ matthuszagh ];
|
||||
platforms = lib.platforms.all;
|
||||
};
|
||||
}
|
|
@ -4,29 +4,27 @@
|
|||
, python3
|
||||
, readline
|
||||
, stdenv
|
||||
, which
|
||||
, yosys
|
||||
, zlib
|
||||
, yosys-symbiflow
|
||||
, uhdm
|
||||
, surelog
|
||||
}: let
|
||||
|
||||
src = fetchFromGitHub {
|
||||
owner = "SymbiFlow";
|
||||
repo = "yosys-symbiflow-plugins";
|
||||
rev = "35c6c33811a8de7c80dff6a7bcf7aa6ec9b21233";
|
||||
hash = "sha256-g5dX9+R+gWt8e7Bhbbg60O9qa+Vi6Ar0M1sHhYlAre8=";
|
||||
owner = "chipsalliance";
|
||||
repo = "yosys-f4pga-plugins";
|
||||
rev = "27208ce08200a5e89e3bd4f466bc68824df38c32";
|
||||
hash = "sha256-S7txjzlIp+idWIfp/DDOznluA3aMFfosMUt5dvi+g44=";
|
||||
};
|
||||
|
||||
version = "2022.01.06";
|
||||
version = "2022.09.27";
|
||||
|
||||
# Supported symbiflow plugins.
|
||||
#
|
||||
# The following are disabled:
|
||||
#
|
||||
# "ql-qlf" builds but fails to load the plugin, so is not currently supported.
|
||||
#
|
||||
# "UHDM" doesn't currently build, as the work to package UHDM and surelog has
|
||||
# not (yet) been undertaken.
|
||||
plugins = [
|
||||
"design_introspection"
|
||||
"fasm"
|
||||
|
@ -36,7 +34,7 @@
|
|||
# "ql-qlf"
|
||||
"sdc"
|
||||
"xdc"
|
||||
# "UHDM"
|
||||
"systemverilog"
|
||||
];
|
||||
|
||||
static_gtest = gtest.dev.overrideAttrs (old: {
|
||||
|
@ -50,8 +48,8 @@ in lib.genAttrs plugins (plugin: stdenv.mkDerivation (rec {
|
|||
inherit src version plugin;
|
||||
enableParallelBuilding = true;
|
||||
|
||||
nativeBuildInputs = [ which python3 ];
|
||||
buildInputs = [ yosys readline zlib ] ;
|
||||
nativeBuildInputs = [ python3 ];
|
||||
buildInputs = [ yosys readline zlib uhdm surelog ];
|
||||
|
||||
# xdc has an incorrect path to a test which has yet to be patched
|
||||
doCheck = plugin != "xdc";
|
||||
|
@ -102,5 +100,3 @@ in lib.genAttrs plugins (plugin: stdenv.mkDerivation (rec {
|
|||
maintainers = with maintainers; [ ollieB thoughtpolice ];
|
||||
};
|
||||
}))
|
||||
|
||||
|
||||
|
|
|
@ -35863,6 +35863,10 @@ with pkgs;
|
|||
|
||||
symfpu = callPackage ../applications/science/logic/symfpu {};
|
||||
|
||||
uhdm = callPackage ../applications/science/logic/uhdm {};
|
||||
|
||||
surelog = callPackage ../applications/science/logic/surelog {};
|
||||
|
||||
mcy = callPackage ../applications/science/logic/mcy {};
|
||||
|
||||
lingeling = callPackage ../applications/science/logic/lingeling {};
|
||||
|
|
Loading…
Reference in a new issue