Merge pull request #239120 from LibreCybernetics/arch-stuff
This commit is contained in:
commit
359e1136a6
2 changed files with 42 additions and 13 deletions
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@ -3,8 +3,15 @@
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rec {
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rec {
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# gcc.arch to its features (as in /proc/cpuinfo)
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# gcc.arch to its features (as in /proc/cpuinfo)
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features = {
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features = {
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# x86_64 Generic
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# Spec: https://gitlab.com/x86-psABIs/x86-64-ABI/
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default = [ ];
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default = [ ];
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x86-64 = [ ];
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x86-64-v2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ];
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x86-64-v3 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "avx" "avx2" "fma" ];
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x86-64-v4 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "avx" "avx2" "avx512" "fma" ];
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# x86_64 Intel
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# x86_64 Intel
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nehalem = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" ];
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westmere = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" ];
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westmere = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" ];
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sandybridge = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
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sandybridge = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
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ivybridge = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
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ivybridge = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
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@ -41,22 +48,32 @@ rec {
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# a superior CPU has all the features of an inferior and is able to build and test code for it
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# a superior CPU has all the features of an inferior and is able to build and test code for it
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inferiors = {
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inferiors = {
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# x86_64 Generic
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default = [ ];
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x86-64 = [ ];
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x86-64-v2 = [ "x86-64" ];
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x86-64-v3 = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
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x86-64-v4 = [ "x86-64-v3" ] ++ inferiors.x86-64-v3;
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# x86_64 Intel
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# x86_64 Intel
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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default = [ ];
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nehalem = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
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westmere = [ ];
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westmere = [ "nehalem" ] ++ inferiors.nehalem;
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sandybridge = [ "westmere" ] ++ inferiors.westmere;
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sandybridge = [ "westmere" ] ++ inferiors.westmere;
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ivybridge = [ "sandybridge" ] ++ inferiors.sandybridge;
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ivybridge = [ "sandybridge" ] ++ inferiors.sandybridge;
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haswell = [ "ivybridge" ] ++ inferiors.ivybridge;
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broadwell = [ "haswell" ] ++ inferiors.haswell;
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haswell = lib.unique ([ "ivybridge" "x86-64-v3" ] ++ inferiors.ivybridge ++ inferiors.x86-64-v3);
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skylake = [ "broadwell" ] ++ inferiors.broadwell;
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broadwell = [ "haswell" ] ++ inferiors.haswell;
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skylake-avx512 = [ "skylake" ] ++ inferiors.skylake;
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skylake = [ "broadwell" ] ++ inferiors.broadwell;
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skylake-avx512 = lib.unique ([ "skylake" "x86-64-v4" ] ++ inferiors.skylake ++ inferiors.x86-64-v4);
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cannonlake = [ "skylake-avx512" ] ++ inferiors.skylake-avx512;
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cannonlake = [ "skylake-avx512" ] ++ inferiors.skylake-avx512;
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icelake-client = [ "cannonlake" ] ++ inferiors.cannonlake;
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icelake-client = [ "cannonlake" ] ++ inferiors.cannonlake;
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icelake-server = [ "icelake-client" ] ++ inferiors.icelake-client;
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icelake-server = [ "icelake-client" ] ++ inferiors.icelake-client;
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cascadelake = [ "skylake-avx512" ] ++ inferiors.cannonlake;
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cascadelake = [ "cannonlake" ] ++ inferiors.cannonlake;
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cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake;
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cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake;
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tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server;
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tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server;
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# CX16 does not exist on alderlake, while it does on nearly all other intel CPUs
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# CX16 does not exist on alderlake, while it does on nearly all other intel CPUs
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alderlake = [ ];
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alderlake = [ ];
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@ -87,10 +104,10 @@ rec {
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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# https://en.wikichip.org/wiki/amd/microarchitectures/zen
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# https://en.wikichip.org/wiki/amd/microarchitectures/zen
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# https://en.wikichip.org/wiki/intel/microarchitectures/skylake
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# https://en.wikichip.org/wiki/intel/microarchitectures/skylake
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znver1 = [ "skylake" ] ++ inferiors.skylake;
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znver1 = [ "skylake" ] ++ inferiors.skylake; # Includes haswell and x86-64-v3
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znver2 = [ "znver1" ] ++ inferiors.znver1;
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znver2 = [ "znver1" ] ++ inferiors.znver1;
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znver3 = [ "znver2" ] ++ inferiors.znver2;
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znver3 = [ "znver2" ] ++ inferiors.znver2;
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znver4 = [ "znver3" ] ++ inferiors.znver3;
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znver4 = lib.unique ([ "znver3" "x86-64-v4" ] ++ inferiors.znver3 ++ inferiors.x86-64-v4);
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# other
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# other
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armv5te = [ ];
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armv5te = [ ];
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@ -106,7 +106,12 @@ let
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isGccArchSupported = arch:
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isGccArchSupported = arch:
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if targetPlatform.isPower then false else # powerpc does not allow -march=
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if targetPlatform.isPower then false else # powerpc does not allow -march=
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if isGNU then
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if isGNU then
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{ # Intel
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{ # Generic
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x86-64-v2 = versionAtLeast ccVersion "11.0";
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x86-64-v3 = versionAtLeast ccVersion "11.0";
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x86-64-v4 = versionAtLeast ccVersion "11.0";
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# Intel
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skylake = versionAtLeast ccVersion "6.0";
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skylake = versionAtLeast ccVersion "6.0";
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skylake-avx512 = versionAtLeast ccVersion "6.0";
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skylake-avx512 = versionAtLeast ccVersion "6.0";
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cannonlake = versionAtLeast ccVersion "8.0";
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cannonlake = versionAtLeast ccVersion "8.0";
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@ -117,6 +122,7 @@ let
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tigerlake = versionAtLeast ccVersion "10.0";
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tigerlake = versionAtLeast ccVersion "10.0";
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knm = versionAtLeast ccVersion "8.0";
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knm = versionAtLeast ccVersion "8.0";
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alderlake = versionAtLeast ccVersion "12.0";
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alderlake = versionAtLeast ccVersion "12.0";
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# AMD
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# AMD
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znver1 = versionAtLeast ccVersion "6.0";
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znver1 = versionAtLeast ccVersion "6.0";
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znver2 = versionAtLeast ccVersion "9.0";
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znver2 = versionAtLeast ccVersion "9.0";
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@ -124,12 +130,18 @@ let
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znver4 = versionAtLeast ccVersion "13.0";
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znver4 = versionAtLeast ccVersion "13.0";
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}.${arch} or true
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}.${arch} or true
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else if isClang then
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else if isClang then
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{ # Intel
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{ #Generic
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x86-64-v2 = versionAtLeast ccVersion "12.0";
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x86-64-v3 = versionAtLeast ccVersion "12.0";
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x86-64-v4 = versionAtLeast ccVersion "12.0";
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# Intel
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cannonlake = versionAtLeast ccVersion "5.0";
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cannonlake = versionAtLeast ccVersion "5.0";
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icelake-client = versionAtLeast ccVersion "7.0";
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icelake-client = versionAtLeast ccVersion "7.0";
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icelake-server = versionAtLeast ccVersion "7.0";
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icelake-server = versionAtLeast ccVersion "7.0";
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knm = versionAtLeast ccVersion "7.0";
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knm = versionAtLeast ccVersion "7.0";
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alderlake = versionAtLeast ccVersion "16.0";
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alderlake = versionAtLeast ccVersion "16.0";
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# AMD
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# AMD
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znver1 = versionAtLeast ccVersion "4.0";
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znver1 = versionAtLeast ccVersion "4.0";
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znver2 = versionAtLeast ccVersion "9.0";
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znver2 = versionAtLeast ccVersion "9.0";
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